Inventor

TAPILY KANDABARA

US53 patents

Patents

50 patents

US10847363B2Nov 24, 2020

Method of selective deposition for forming fully self-aligned vias

TOKYO ELECTRON LTD39 citations98

US10586765B2Mar 10, 2020

Buried power rails

TOKYO ELECTRON LTD62 citations98

US11101173B2Aug 24, 2021

Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same

TOKYO ELECTRON LTD11 citations94

US10916472B2Feb 9, 2021

Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same

TOKYO ELECTRON LTD14 citations94

US10770479B2Sep 8, 2020

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

TOKYO ELECTRON LTD4 citations84

US11114381B2Sep 7, 2021

Power distribution network for 3D logic and memory

TOKYO ELECTRON LTD7 citations84

US10930764B2Feb 23, 2021

Extension region for a semiconductor device

TOKYO ELECTRON LTD6 citations84

US10727057B2Jul 28, 2020

Platform and method of operating for integrated end-to-end self-aligned multi-patterning process

TOKYO ELECTRON LTD10 citations83

US11616053B2Mar 28, 2023

Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device

TOKYO ELECTRON LTD4 citations75

US11264289B2Mar 1, 2022

Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

TOKYO ELECTRON LTD2 citations73

US11264274B2Mar 1, 2022

Reverse contact and silicide process for three-dimensional logic devices

TOKYO ELECTRON LTD5 citations73

US11152207B2Oct 19, 2021

Method of forming titanium nitride films with (200) crystallographic texture

TOKYO ELECTRON LTD2 citations73

US11031287B2Jun 8, 2021

Fully self-aligned via with selective bilayer dielectric regrowth

TOKYO ELECTRON LTD3 citations73

US10886173B2Jan 5, 2021

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

TOKYO ELECTRON LTD2 citations73

US10847424B2Nov 24, 2020

Method for forming a nanowire device

TOKYO ELECTRON LTD4 citations72

US11024535B2Jun 1, 2021

Method for filling recessed features in semiconductor devices with a low-resistivity metal

TOKYO ELECTRON LTD4 citations71

US10991881B2Apr 27, 2021

Method for controlling the forming voltage in resistive random access memory devices

TOKYO ELECTRON LTD2 citations71

US10734278B2Aug 4, 2020

Method of protecting low-K layers

TOKYO ELECTRON LTD3 citations68

US12336274B2Jun 17, 2025

Self-aligned method for vertical recess for 3D device integration

TOKYO ELECTRON LTD1 citations64

US11901360B2Feb 13, 2024

Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory

TOKYO ELECTRON LTD0 citations63

US11769677B2Sep 26, 2023

Substrate processing tool with integrated metrology and method of using

TOKYO ELECTRON LTD0 citations63

US11705369B2Jul 18, 2023

Fully self-aligned via with selective bilayer dielectric regrowth

TOKYO ELECTRON LTD0 citations63

US11676968B2Jun 13, 2023

Coaxial contacts for 3D logic and memory

TOKYO ELECTRON LTD0 citations63

US11616020B2Mar 28, 2023

Power distribution network for 3D logic and memory

TOKYO ELECTRON LTD0 citations63

US11264254B2Mar 1, 2022

Substrate processing tool with integrated metrology and method of using

TOKYO ELECTRON LTD0 citations63

US11251200B2Feb 15, 2022

Coaxial contacts for 3D logic and memory

TOKYO ELECTRON LTD0 citations63

US11217583B2Jan 4, 2022

Architecture design of monolithically integrated 3D CMOS logic and memory

TOKYO ELECTRON LTD1 citations63

US12417925B2Sep 16, 2025

Method of conductive material deposition

TOKYO ELECTRON LTD0 citations62

US12020990B2Jun 25, 2024

Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks

TOKYO ELECTRON LTD0 citations62

US11658068B2May 23, 2023

Method of selective deposition for forming fully self-aligned vias

TOKYO ELECTRON LTD0 citations62

US11646227B2May 9, 2023

Method of forming a semiconductor device with air gaps for low capacitance interconnects

TOKYO ELECTRON LTD0 citations62

US11594451B2Feb 28, 2023

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

TOKYO ELECTRON LTD0 citations62

US11398379B2Jul 26, 2022

Platform and method of operating for integrated end-to-end self-aligned multi-patterning process

TOKYO ELECTRON LTD0 citations62

US11251077B2Feb 15, 2022

Method of forming a semiconductor device with air gaps for low capacitance interconnects

TOKYO ELECTRON LTD1 citations62

US10923394B2Feb 16, 2021

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

TOKYO ELECTRON LTD0 citations62

US11700778B2Jul 11, 2023

Method for controlling the forming voltage in resistive random access memory devices

TOKYO ELECTRON LTD0 citations61

US11621190B2Apr 4, 2023

Method for filling recessed features in semiconductor devices with a low-resistivity metal

TOKYO ELECTRON LTD0 citations61

US11170992B2Nov 9, 2021

Area selective deposition for cap layer formation in advanced contacts

TOKYO ELECTRON LTD1 citations61

US11322401B2May 3, 2022

Reverse contact and silicide process for three-dimensional semiconductor devices

TOKYO ELECTRON LTD1 citations60

US11302588B2Apr 12, 2022

Platform and method of operating for integrated end-to-end area-selective deposition process

TOKYO ELECTRON LTD1 citations58

US11152268B2Oct 19, 2021

Platform and method of operating for integrated end-to-end area-selective deposition process

TOKYO ELECTRON LTD0 citations58

US12568651B2Mar 3, 2026

Semiconductor structure having stacked gates and method of manufacture thereof

TOKYO ELECTRON LTD0 citations52

US11335599B2May 17, 2022

Self-aligned contacts for 3D logic and memory

TOKYO ELECTRON LTD0 citations52

US10586734B2Mar 10, 2020

Method of selective film deposition for forming fully self-aligned vias

TOKYO ELECTRON LTD0 citations52

US12564027B2Feb 24, 2026

Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals

TOKYO ELECTRON LTD0 citations51

US11532517B2Dec 20, 2022

Localized etch stop layer

TOKYO ELECTRON LTD0 citations51

US12588435B2Mar 24, 2026

Selective inhibition for selective metal deposition

TOKYO ELECTRON LTD0 citations50

Showing the top 50 of 53 patents by PatentIndex Score.

TAPILY KANDABARA

Patents

Method of selective deposition for forming fully self-aligned vias

Buried power rails

Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same

Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same

Three-dimensional device and method of forming the same

Extension region for a semiconductor device

Three-dimensional semiconductor device and method of fabrication

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Power distribution network for 3D logic and memory

Extension region for a semiconductor device

Platform and method of operating for integrated end-to-end self-aligned multi-patterning process

Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device

Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

Reverse contact and silicide process for three-dimensional logic devices

Method of forming titanium nitride films with (200) crystallographic texture

Fully self-aligned via with selective bilayer dielectric regrowth

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Method for forming a nanowire device

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Method for controlling the forming voltage in resistive random access memory devices

Method of protecting low-K layers

Self-aligned method for vertical recess for 3D device integration

Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory

Substrate processing tool with integrated metrology and method of using

Fully self-aligned via with selective bilayer dielectric regrowth

Coaxial contacts for 3D logic and memory

Power distribution network for 3D logic and memory

Substrate processing tool with integrated metrology and method of using

Coaxial contacts for 3D logic and memory

Architecture design of monolithically integrated 3D CMOS logic and memory

Method of conductive material deposition

Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks

Method of selective deposition for forming fully self-aligned vias

Method of forming a semiconductor device with air gaps for low capacitance interconnects

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Platform and method of operating for integrated end-to-end self-aligned multi-patterning process

Method of forming a semiconductor device with air gaps for low capacitance interconnects

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Method for controlling the forming voltage in resistive random access memory devices

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Area selective deposition for cap layer formation in advanced contacts

Reverse contact and silicide process for three-dimensional semiconductor devices

Platform and method of operating for integrated end-to-end area-selective deposition process

Platform and method of operating for integrated end-to-end area-selective deposition process

Semiconductor structure having stacked gates and method of manufacture thereof

Self-aligned contacts for 3D logic and memory

Method of selective film deposition for forming fully self-aligned vias

Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals

Localized etch stop layer

Selective inhibition for selective metal deposition