Inventor

SUNDARARAMAN RAMACHARAN

US33 patents

⚠️ This page may combine multiple inventors who share the name “SUNDARARAMAN RAMACHARAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUNDARARAMAN RAMACHARAN

MARVELL ASIA PTE LTD

System and method to manage power throttling

System and methods for firmware update mechanism

System and methods for firmware security mechanism

System and method for hardware-based register protection mechanism

System and method to manage power to a desired power profile

System and methods for hardware-based PCIe link up based on post silicon characterization

System and method for memory region protection

Address interleaving for machine learning

Address interleaving for machine learning

System and method to manage power throttling

System and method to manage power to a desired power profile

System and methods for hardware-based PCIe link up based on post silicon characterization

System and method for SRAM less electronic device bootup using cache

System and methods for latency reduction for fuse reload post reset

INTEL CORP

Providing extended cache replacement state information

Cross-die interface snoop or global observation message ordering

PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory

Techniques to support multiple protocols between computer system interconnects

Memory sequencing with coherent and non-coherent sub-systems

Techniques to support multiple protocols between computer system interconnects

Techniques to support mulitple interconnect protocols for an interconnect

Memory sequencing with coherent and non-coherent sub-systems

System and method for optimizing memory bus bandwidth utilization by request classification and ordering

CHANG STEVEN S

Reset of multi-core processing system

Reset of processing core in multi-core processing system

Boot strap processor assignment for a multi-core processing unit

Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit

QUALCOMM INC

Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures

Dynamically reconfigured redundant lanes in a communication interface circuit between chiplets to increase redundancy when the probability of failure favors a particular communication direction

Mechanism to improve the reliability of sideband in chiplets

SUNDARARAMAN RAMACHARAN

Accessing control and status register (CSR)

FRYMAN JOSHUA B

Adaptively handling remote atomic execution based upon contention prediction

CORBAL JESUS

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