Inventor

VAN DOREN STEPHEN R

US73 patents

⚠️ This page may combine multiple inventors who share the name “VAN DOREN STEPHEN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN DOREN STEPHEN R

INTEL CORP

Techniques to support multiple interconnect protocols for a common set of interconnect connectors

Techniques for managing access to hardware accelerator memory

Systems, methods, and apparatuses for heterogeneous computing

Remote atomic operations in multi-socket systems

Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Coherent accelerator fabric controller

Multi-core communication acceleration using hardware queue device

PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory

Remote atomic operations in multi-socket systems

Systems, methods, and apparatuses for heterogeneous computing

Techniques to support multiple protocols between computer system interconnects

Non-posted write transactions for a computer bus

Spatial and temporal merging of remote atomic operations

Method and apparatus to provide secure application execution

Techniques to support multiple interconnect protocols for a common set of interconnect connectors

HEWLETT PACKARD DEVELOPMENT CO

System and method for responses between different cache coherency protocols

Mechanism for resolving ambiguous invalidates in a computer system

Mechanism for resolving ambiguous invalidates in a computer system

Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation

Transaction references for requests in a multi-processor network

System and method to facilitate ordering point migration

System and method for conflict responses in a cache coherency protocol with ordering point migration

System and method for blocking data responses

System and method for read migratory optimization in a cache coherency protocol

Linked-list early race resolution mechanism

System and method for avoiding deadlock

Retry-based late race resolution mechanism for a computer system

System and method to facilitate ordering point migration to memory

System and method for conflict responses in a cache coherency protocol

Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss

Coherent signal in a multi-processor system

DIGITAL EQUIPMENT CORP

Mechanism for reducing latency of memory barrier operations on a multiprocessor system

Method and apparatus for adaptive memory access

Method and apparatus for performing atomic transactions in a shared memory multi processor system

Distributed data bus sequencing for a system bus with separate address and data bus protocols

Distributed data bus sequencing for a system bus with separate address and data bus protocols

Memory bank addressing scheme

Arbitration unit which requests control of the system bus prior to determining whether such control is required

System bus with separate address and data bus protocols

COMPAQ COMPUTER CORP

Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system

Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches

Mechanism for optimizing generation of commit-signals in a distributed shared-memory system

Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor

Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches

MCKEEN FRANCIS X

Method and apparatus to provide secure application execution

(unassigned)

System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information

TIERNEY GREGORY EDWARD

System and method for creating ordering points

STEELY JR SIMON C

System and method for non-migratory requests in a cache coherency protocol