Inventor

WU HUAQIANG

CN45 patents

⚠️ This page may combine multiple inventors who share the name “WU HUAQIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU HUAQIANG

UNIV TSINGHUA

Video stitching method and device

Neuron simulation circuit and neural network apparatus

Memristor and preparation method thereof

Nanowire transistor and manufacturing method thereof

Resistive random access memory and manufacturing method thereof

Conductive paste, preparation method thereof, and preparation method of conductive film

Circuit structure and driving method thereof, chip and authentication method thereof, and electronic device

Compilation method, apparatus, computing device and medium

Memory computing integrated device and calibration method thereof

Parallel acceleration method for memristor-based neural network, parallel acceleration processor based on memristor-based neural network and parallel acceleration device based on memristor-based neural network

Signal processing device and signal processing method

Resistive random access memory and manufacturing method thereof

In-memory computing processor, processing system, processing apparatus, deployment method of algorithm model

Data processing method based on memristor array and electronic apparatus

Signal processing apparatus and signal processing method

Method for preparing a molybdenum disulfide film used in a field emission device

Neural network and its information processing method, information processing system

Generative adversarial network device and training method thereof

Circuit structure and driving method thereof, neural network

Operation method of resistive random access memory and resistive random access memory device

Distributed amplifier

SPANSION LLC

Triple poly-si replacement scheme for memory devices

Split charge storage node inner spacer process

HTO offset spacers and dip off process to define junction

Split charge storage node outer spacer process

ORO and ORPRO with bit line trench to suppress transport program disturb

Sacrificial nitride and gate replacement

Split charge storage node outer spacer process

HTO offset and BL trench process for memory device to improve device performance

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

CORNELL RES FOUNDATION INC

Group III nitride compositions

Method of making Group III nitrides

Group III nitride coatings and methods

GaN bulk growth by Ga vapor transport

CHENG NING

HTO offset for long Leffective, better device performance

Oro and orpro with bit line trench to suppress transport program disturb

HTO offset and BL trench process for memory device to improve device performance

LEE CHUNGHO

Gate replacement with top oxide regrowth for the top oxide improvement

Sacrificial nitride and gate replacement

HUAWEI TECH CO LTD

Storage device and data writing method

Neural network circuit and neural network system

CYPRESS SEMICONDUCTOR CORP

HTO offset for long leffective, better device performance

SHANDONG HOLLY PHARMACEUTICAL CO LTD

Method for preparing amantadine

WU HUAQIANG

Implement method and device of terminal call firewall