Inventor

PEKNY THEODORE T

US105 patents

⚠️ This page may combine multiple inventors who share the name “PEKNY THEODORE T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PEKNY THEODORE T

MICRON TECHNOLOGY INC

Memory array with a pair of memory-cell strings to a single conductive pillar

Memory device including redundancy routine for correcting random errors

Apparatuses including multiple read modes and methods for same

Apparatuses including multiple read modes and methods for same

Apparatuses including multiple read modes and methods for same

Apparatuses and methods for concurrently accessing different memory planes of a memory

Memory device internal parameter reliability

Low voltage sense amplifier for operation under a reduced bit line bias voltage

High voltage regulator for low voltage integrated circuit processes

Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation

Method and apparatus for trimming non-volatile memory cells

System and method for data read of a synchronous serial interface NAND

High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices

Non-volatile memory with peak current noise reduction

Programming flash memories

Programming flash memories

Apparatuses including multiple read modes and methods for same

Apparatuses including multiple read modes and methods for same

Systems including memory cells on opposing sides of a pillar

Memory devices having special mode access using a serial message

Apparatuses including multiple read modes and methods for same

Memory devices having special mode access

Apparatuses and methods for concurrently accessing different memory planes of a memory

Memory devices having special mode access using a serial message

System and method for data read of a synchronous serial interface NAND

Storing operational information in an array of memory cells

Test mode for multi-chip integrated circuit packages

Power on reset circuitry in electronic systems

Memory device with non-volatile reference memory cell trimming capabilities

Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation

Clock regulation scheme for varying loads

Apparatuses and methods for concurrently accessing different memory planes of a memory

Programming flash memories

Low voltage sense amplifier for operation under a reduced bit line bias voltage

Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation

Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation

PEKNY THEODORE T

System and method for setting access and modification for synchronous serial interface NAND

System and method for data read of a synchronous serial interface NAND

Boot block features in synchronous serial interface NAND

Outputting a particular data quantization from memory

Storing operational information in an array of memory cells

Serial interface NAND

Methods of forming a memory array with a pair of memory-cell strings to a single conductive pillar

System and method for data read of a synchronous serial interface NAND

SPI NAND protected mode entry methodology

Method for operating a NAND flash memory device in multiple operational modes

MOSCHIANO VIOLANTE

Threshold voltage compensation in a multilevel memory

Memory apparatus, systems, and methods

TEXAS INSTRUMENTS INC

Leakage tolerant sense amplifier

FEELEY PETER S

Method for detecting flash program failures