Inventor

SUNDAR VIGNESH

US43 patents

⚠️ This page may combine multiple inventors who share the name “SUNDAR VIGNESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUNDAR VIGNESH

TAIWAN SEMICONDUCTOR MFG CO LTD

Dual magnetic tunnel junction devices for magnetic random access memory (MRAM)

Nitride capping layer for spin torque transfer (STT) magnetoresistive random access memory (MRAM)

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive R-deposition

Dual magnetic tunnel junction (DMTJ) stack design

Nitride capping layer for spin torque transfer (STT)-magnetoresistive random access memory (MRAM)

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

Post treatment to reduce shunting devices for physical etching process

MTJ device performance by adding stress modulation layer to MTJ device structure

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive re-deposition

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive R-deposition

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

Combined physical and chemical etch to reduce magnetic tunnel junction (MTJ) sidewall damage

Method for fabricating a magnetic tunneling junction (MTJ) structure

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

Dual magnetic tunnel junction devices for magnetic random access memory (MRAM)

Multilayer structure for reducing film roughness in magnetic devices

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive re-deposition

MTJ device performance by adding stress modulation layer to MTJ device structure

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

Dual magnetic tunnel junction (DMTJ) stack design

Cooling for PMA (perpendicular magnetic anisotropy) enhancement of STT-MRAM (spin-torque transfer-magnetic random access memory) devices

Post treatment to reduce shunting devices for physical etching process

Nitride capping layer for spin torque transfer (STT) magnetoresistive random access memory (MRAM)

MTJ device performance by adding stress modulation layer to mtj device structure

Dual magnetic tunnel junction devices for magnetic random access memory (MRAM)

Post treatment to reduce shunting devices for physical etching process

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

Combined physical and chemical etch to reduce magnetic tunnel junction (MTJ) sidewall damage

Post treatment to reduce shunting devices for physical etching process

HEADWAY TECH INC

Dielectric encapsulation layer for magnetic tunnel junction (MTJ) devices using radio frequency (RF) sputtering

Ion beam etching process design to minimize sidewall re-deposition

Reduce intermixing on MTJ sidewall by oxidation

Cooling for PMA (perpendicular magnetic anisotropy) enhancement of STT-MRAM (spin torque transfer-magnetic random access memory) devices

Multilayer structure for reducing film roughness in magnetic devices

Nitride diffusion barrier structure for spintronic applications

Nitride diffusion barrier structure for spintronic applications

Etching and encapsulation scheme for magnetic tunnel junction fabrication

Etching and encapsulation scheme for magnetic tunnel junction fabrication

Method to integrate MRAM devices to the interconnects of 30nm and beyond CMOS technologies