Inventor
HOOK TERENCE
US16 patents
⚠️ This page may combine multiple inventors who share the name “HOOK TERENCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
14 patentsUS10128347B2Nov 13, 2018
Gate-all-around field effect transistor having multiple threshold voltages
IBM6 citations84
US10586854B2Mar 10, 2020
Gate-all-around field effect transistor having multiple threshold voltages
IBM2 citations73
US12557320B2Feb 17, 2026
FVBP without backside Si recess
IBM0 citations62
US12550448B2Feb 10, 2026
Protection diode to prevent charge damage during MOL
IBM0 citations62
US12527076B2Jan 13, 2026
Stacked FET vertical diode
IBM0 citations62
US12040250B2Jul 16, 2024
Heat pipe for vertically stacked field effect transistors
IBM0 citations62
US12015069B2Jun 18, 2024
Gate-all-around field effect transistor having multiple threshold voltages
IBM0 citations62
US12571837B2Mar 10, 2026
Semiconductor device with a protective diode connected to a fuse
IBM0 citations60
US12230629B2Feb 18, 2025
Size-efficient mitigation of latchup and latchup propagation
IBM0 citations60
US11663391B2May 30, 2023
Latch-up avoidance for sea-of-gates
IBM0 citations56
US12557353B2Feb 17, 2026
Method and structure for a logic device and another device
IBM0 citations52
US11245020B2Feb 8, 2022
Gate-all-around field effect transistor having multiple threshold voltages
IBM0 citations52
US12268026B2Apr 1, 2025
High aspect ratio contact structure with multiple metal stacks
IBM0 citations51
US12176289B2Dec 24, 2024
Semiconductor device design mitigating latch-up
IBM0 citations50