Inventor

SCHOENFELD AARON M

US41 patents

⚠️ This page may combine multiple inventors who share the name “SCHOENFELD AARON M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHOENFELD AARON M

MICRON TECHNOLOGY INC

Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers

Method and apparatus for determining digital delay line entry point

Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal

Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Controlling impedances of an integrated circuit

Device and method for electrostatic discharge protection of a circuit device

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

Method and apparatus for determining digital delay line entry point

Method and apparatus for output data synchronization with system clock in DDR

Semiconductor component with adjustment circuitry

Dynamically centered setup-time and hold-time window

Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

Device, system and method for reducing power in a memory device during standby modes

Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

Device and method for electrostatic discharge protection of a circuit device

Circuit and method for reducing power in a memory device during standby modes

Method and apparatus for improving output skew for synchronous integrated circuits

Device, system and method for reducing power in a memory device during standby modes

Method and unit for selectively enabling an input buffer based on an indication of a clock transition

Method for fabricating a semiconductor component

Semiconductor component with electrical characteristic adjustment circuitry

Controlling impedances of an integrated circuit

Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Apparatus for measuring parasitic capacitance and inductance of I/O leads on electrical component using a network analyzer

Method and unit for buffer control

Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration

Device and method for electrostatic discharge protection of a circuit device

Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

Method and apparatus for decoupling conductive portions of a microelectronic device package

Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Apparatus and methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer

Method and apparatus for decoupling conductive portions of a microelectronic device package

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

ROUND ROCK RES LLC

Method and apparatus for output data synchronization with system clock in DDR

Circuit and method for reducing power in a memory device during standby modes

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation