Inventor

OSBORNE RANDY B

US53 patents

⚠️ This page may combine multiple inventors who share the name “OSBORNE RANDY B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OSBORNE RANDY B

INTEL CORP

Method and apparatus to counter mismatched burst lengths

Prefetching data for peripheral component interconnect devices

Identical chips with different operations in a system

Method and system to improve prefetching operations

Method and apparatus for memory access scheduling to reduce memory access latency

Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect

Multiple rank high bandwidth memory

Memory micro-tiling

Method and apparatus for implicit DRAM precharge

Method and apparatus for read launch optimizations in memory interconnect

High performance memory device-state aware chipset prefetcher

Memory system with both single and consolidated commands

Direct bonding in microelectronic assemblies

System and method for improved half-duplex bus performance

Memory post-write page closing apparatus and method

High performance chipset prefetcher for interleaved channels

Automatic hardware ZLW insertion for IPU image streams

Dynamic parity inversion for I/O interconnects

Memory post-write page closing apparatus and method

Chips providing single and consolidated commands

Scalable schedulers for memory controllers

Memory micro-tiling

Memory systems with memory chips down and up

Method and apparatus for selective DRAM precharge

Method and apparatus for hublink read return streaming

Method and apparatus for single wire signaling of request types in a computer system having a point to point half duplex interconnect

Dynamic parity inversion for I/O interconnects

Dynamic parity inversion for I/O interconnects

Multiple rank high bandwidth memory

MITSUBISHI ELECTRIC INF TECH

Real-time PC based volume rendering system

Computer network interface and network protocol with direct deposit messaging

Network interface having support for message processing and an interface to a message coprocessor

Network interface

Network interface having support for allowing remote operations with reply that bypass host computer interaction

Traffic shaping and ABR flow control

ATM local area network switch with dual queues

Computer system with a network interface which multiplexes a set of registers among several transmit and receive queues

Host computer and network interface using a two-dimensional per-application list of application level free buffers

TERARECON INC

Method for rendering sections of a volume data set

Volume rendering pipelines

Method for rendering mini blocks of a volume data set

Super-sampling and gradient estimation in a ray-casting volume rendering system

CHINNASWAMY KUMAR K

Hybrid memory architectures

Hybrid memory architectures

THOMAS THOMAS P

On-package input/output clustered interface having full and half-duplex modes

Interconnection of multiple chips in a package

INTEL CORPORATIOON

Method and apparatus for out of order memory scheduling

BAINS KULJIT S

Dynamic random access memory with shadow writes

ABRAHAM PHILIP

Scalable schedulers for memory controllers

OSBORNE RANDY B

Mechanisms for clock gating