Inventor

MULLARKEY PATRICK J

US73 patents

⚠️ This page may combine multiple inventors who share the name “MULLARKEY PATRICK J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MULLARKEY PATRICK J

MICRON TECHNOLOGY INC

Computer system having memory device with adjustable data clocking

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

Method and apparatus for storage of test results within an integrated circuit

Method and apparatus for storage of test results within an integrated circuit

Computer system having memory device with adjustable data clocking using pass gates

Apparatus for adjusting delay of a clock signal relative to a data signal

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

Synchronous memory device having an adjustable data clocking circuit

Method and apparatus for adjusting data timing by delaying clock signal

ROM-embedded-DRAM

Circuit and method for refreshing data stored in a memory cell

Rom-embedded-DRAM

Circuit for programming antifuse bits

Apparatus for disabling and re-enabling access to IC test functions

Self current limiting antifuse circuit

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

Apparatus and method for increasing test flexibility of a memory device

Method and apparatus for multiple row activation in memory devices

Circuit and method for refreshing data stored in a memory cell

Circuit and method for refreshing data stored in a memory cell

Memory device with command buffer

Apparatus and method for increasing test flexibility of a memory device

Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing

Method and apparatus for multiple row activation in memory devices

Memory device with MOS transistors having bodies biased by temperature-compensated voltage

Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing

Memory device with MOS transistors having bodies biased by temperature-compensated voltage

Apparatus and method disabling and re-enabling access to IC test functions

Method and apparatus for checking the resistance of programmable elements

Circuit for programming antifuse bits

Efficient Vccp supply with regulation for voltage control

Reprogrammable option select circuit

Self current limiting antifuse circuit

Circuit for programming antifuse bits

Circuit for programming antifuse bits

Circuit for programming antifuse bits

Method for testing a memory device having different number of data pads than the tester

Memory device with command buffer that allows internal command buffer jumps

Method for disabling and re-enabling access to IC test functions

ROM-embedded-DRAM

Method and apparatus for multiple row activation in memory devices

Apparatus and method for disabling and re-enabling access to IC test functions

Row decoded biasing of sense amplifier for improved one&#39;s margin

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS

Row decoded biasing of sense amplifier for improved one&#39;s margin

Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing

Row decoded biasing of sense amplifier for improved one&#39;s margin

Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing

MICRON SEMICONDUCTOR INC

Low-current polysilicon fuse

Row decoded biasing of sense amplifier for improved one's margin

Row decoded biasing of sense amplifier for improved one's margin

Row decoded biasing of sense amplifier for improved one's margin