Inventor
HEDBERG ERIK L
US38 patents
⚠️ This page may combine multiple inventors who share the name “HEDBERG ERIK L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
36 patentsUS5870350AFeb 9, 1999
High performance, high bandwidth memory bus architecture utilizing SDRAMs
IBM317 citations99
US5563086AOct 8, 1996
Integrated memory cube, structure and fabrication
IBM195 citations99
US5561622AOct 1, 1996
Integrated memory cube structure
IBM250 citations99
US6420925B1Jul 16, 2002
Programmable latch device with integrated programmable element
IBM91 citations98
US6396120B1May 28, 2002
Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application
IBM84 citations98
US6255899B1Jul 3, 2001
Method and apparatus for increasing interchip communications rates
IBM136 citations98
US6233184B1May 15, 2001
Structures for wafer level test and burn-in
IBM102 citations98
US5896404AApr 20, 1999
Programmable burst length DRAM
IBM130 citations98
US5313424AMay 17, 1994
Module level electronic redundancy
IBM157 citations98
US5502667AMar 26, 1996
Integrated multichip memory module structure
IBM291 citations97
US5446695AAug 29, 1995
Memory device with programmable self-refreshing and testing methods therefore
IBM119 citations97
US6633055B2Oct 14, 2003
Electronic fuse structure and method of manufacturing
IBM69 citations96
US6574763B1Jun 3, 2003
Method and apparatus for semiconductor integrated circuit testing and burn-in
IBM61 citations96
US6518112B2Feb 11, 2003
High performance, low power vertical integrated CMOS devices
IBM67 citations96
US6297531B2Oct 2, 2001
High performance, low power vertical integrated CMOS devices
IBM73 citations96
US6177807B1Jan 23, 2001
High frequency valid data strobe
IBM55 citations96
US6178517B1Jan 23, 2001
High bandwidth DRAM with low operating power modes
IBM60 citations96
US6388305B1May 14, 2002
Electrically programmable antifuses and methods for forming the same
IBM78 citations95
US6567950B1May 20, 2003
Dynamically replacing a failed chip
IBM31 citations93
US6137129AOct 24, 2000
High performance direct coupled FET memory cell
IBM27 citations93
US6070262AMay 30, 2000
Reconfigurable I/O DRAM
IBM36 citations93
US6426904B2Jul 30, 2002
Structures for wafer level test and burn-in
IBM43 citations92
US4730122AMar 8, 1988
Power supply adapter systems
IBM34 citations92
US5019772AMay 28, 1991
Test selection techniques
IBM26 citations91
US7300825B2Nov 27, 2007
Customizing back end of the line interconnects
IBM10 citations83
US6812122B2Nov 2, 2004
Method for forming a voltage programming element
IBM16 citations83
US6426530B1Jul 30, 2002
High performance direct coupled FET memory cell
IBM8 citations74
US6065093AMay 16, 2000
High bandwidth narrow I/O memory device with command stacking
IBM10 citations74
US9536796B2Jan 3, 2017
Multiple manufacturing line qualification
IBM2 citations73
US5969997AOct 19, 1999
Narrow data width DRAM with low latency page-hit operations
IBM8 citations73
US8024513B2Sep 20, 2011
Method and system for implementing dynamic refresh protocols for DRAM based cache
IBM5 citations62
US7701035B2Apr 20, 2010
Laser fuse structures for high power applications
IBM5 citations62
US6570254B1May 27, 2003
Electrical mask identification of memory modules
IBM2 citations59
US6268228B1Jul 31, 2001
Electrical mask identification of memory modules
IBM0 citations49
US8966431B2Feb 24, 2015
Semiconductor timing improvement
IBM1 citations48
US9514999B2Dec 6, 2016
Systems and methods for semiconductor line scribe line centering
IBM0 citations40