Inventor

KHAMANKAR RAJESH

US38 patents

⚠️ This page may combine multiple inventors who share the name “KHAMANKAR RAJESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHAMANKAR RAJESH

TEXAS INSTRUMENTS INC

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

Method for non-thermally nitrided gate formation for high voltage devices

Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

Method for forming integrated circuit capacitor and memory

Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

PMD liner nitride films and fabrication methods for improved NMOS performance

Transistor fabrication methods using reduced width sidewall spacers

Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

Integrated circuit capacitor and memory

Method for forming integrated circuit capacitor and memory

Gate structure and method

Gate structure and method

Transistor fabrication methods using dual sidewall spacers

Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation

Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures

Hexagonally symmetric integrated circuit cell

Reliable high voltage gate dielectric layers using a dual nitridation process

CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers

Reliable high voltage gate dielectric layers using a dual nitridation process

Post high voltage gate dielectric pattern plasma surface treatment

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

Nitrogen based implants for defect reduction in strained silicon

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

Gate dielectric having a flat nitrogen profile and method of manufacture therefor

High performance CMOS transistors using PMD liner stress

Hexagonally symmetric integrated circuit cell

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance

CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers

Dual-gate integrated circuit semiconductor device

Thermal treatment of nitrided oxide to improve negative bias thermal instability

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

Method for improving a physical property defect value of a gate dielectric

BU HAOWEN

Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

High performance CMOS transistors using PMD liner stress

PMD liner nitride films and fabrication methods for improved NMOS performance

CHAKRAVARTHI SRINIVASAN

Nitrogen based implants for defect reduction in strained silicon