Inventor
JOSEPH DOUGLAS J
US31 patents
⚠️ This page may combine multiple inventors who share the name “JOSEPH DOUGLAS J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
27 patentsUS6721806B2Apr 13, 2004
Remote direct memory access enabled network interface controller switchover and switchback support
IBM155 citations98
US6449699B2Sep 10, 2002
Apparatus and method for partitioned memory protection in cache coherent symmetric multiprocessor systems
IBM109 citations98
US7299266B2Nov 20, 2007
Memory management offload for RDMA enabled network adapters
IBM123 citations97
US6628615B1Sep 30, 2003
Two level virtual channels
IBM99 citations97
US6735647B2May 11, 2004
Data reordering mechanism for high performance networks
IBM65 citations96
US6337852B1Jan 8, 2002
Flow control system using control information of a message for initiating retransmission of data portion when buffer is available
IBM47 citations96
US6480897B1Nov 12, 2002
Optimistic transmission flow control including receiver data discards upon inadequate buffering condition
IBM18 citations92
US6405292B1Jun 11, 2002
Split pending buffer with concurrent access of requests and responses to fully associative and indexed components
IBM22 citations92
US6338123B2Jan 8, 2002
Complete and concise remote (CCR) directory
IBM27 citations92
US9298395B2Mar 29, 2016
Memory system connector
IBM10 citations84
US7912988B2Mar 22, 2011
Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms
IBM11 citations84
US7721182B2May 18, 2010
Soft error protection in individual memory devices
IBM12 citations84
US7519650B2Apr 14, 2009
Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms
IBM7 citations74
US6823437B2Nov 23, 2004
Lazy deregistration protocol for a split socket stack
IBM11 citations74
US5506993AApr 9, 1996
Message packet transmitter
IBM13 citations74
US6338091B1Jan 8, 2002
System for optimistic transmission flow control including receiver data discards upon inadequate buffering condition
IBM6 citations73
US10579425B1Mar 3, 2020
Power aware scheduling of requests in 3D chip stack
IBM4 citations68
US7818362B2Oct 19, 2010
Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms
IBM4 citations63
US7408945B2Aug 5, 2008
Use of hardware to manage dependencies between groups of network data packets
IBM2 citations62
US7099997B2Aug 29, 2006
Read-modify-write avoidance using a boundary word storage mechanism
IBM4 citations62
US6721858B1Apr 13, 2004
Parallel implementation of protocol engines based on memory partitioning
IBM5 citations62
US11169848B2Nov 9, 2021
Power aware scheduling of requests in 3D chip stack
IBM0 citations58
US9684629B2Jun 20, 2017
Efficient calibration of a low power parallel data communications channel
IBM1 citations52
US9001842B2Apr 7, 2015
Parallel receiver interface with receiver redundancy
IBM0 citations52
US7724757B2May 25, 2010
Use of hardware to manage dependencies between groups of network data packets
IBM0 citations51
US7353429B2Apr 1, 2008
System and method using hardware buffers for processing microcode trace data
IBM0 citations43
US10740116B2Aug 11, 2020
Three-dimensional chip-based regular expression scanner
IBM0 citations34