Inventor
PHAM TUAN D
US20 patents
⚠️ This page may combine multiple inventors who share the name “PHAM TUAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED MICRO DEVICES INC
11 patentsUS5998301ADec 7, 1999
Method and system for providing tapered shallow trench isolation structure profile
ADVANCED MICRO DEVICES INC51 citations96
US5966618AOct 12, 1999
Method of forming dual field isolation structures
ADVANCED MICRO DEVICES INC25 citations92
US6537866B1Mar 25, 2003
Method of forming narrow insulating spacers for use in reducing minimum component size
ADVANCED MICRO DEVICES INC7 citations74
US6248627B1Jun 19, 2001
Method for protecting gate edges from charge gain/loss in semiconductor device
ADVANCED MICRO DEVICES INC8 citations74
US5920786AJul 6, 1999
Method for fabricating shallow isolation trenches using angular photoresist profiles to create sloped isolation trench walls
ADVANCED MICRO DEVICES INC16 citations74
US6798002B1Sep 28, 2004
Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming
ADVANCED MICRO DEVICES INC10 citations73
US6034394AMar 7, 2000
Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices
ADVANCED MICRO DEVICES INC7 citations72
US6455373B1Sep 24, 2002
Semiconductor device having gate edges protected from charge gain/loss
ADVANCED MICRO DEVICES INC4 citations63
US7012008B1Mar 14, 2006
Dual spacer process for non-volatile memory devices
ADVANCED MICRO DEVICES INC3 citations62
US6274433B1Aug 14, 2001
Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices
ADVANCED MICRO DEVICES INC2 citations61
US6808996B1Oct 26, 2004
Method for protecting gate edges from charge gain/loss in semiconductor device
ADVANCED MICRO DEVICES INC1 citations52
SANDISK CORP
5 patentsUS7723186B2May 25, 2010
Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
SANDISK CORP26 citations92
US7541240B2Jun 2, 2009
Integration process flow for flash devices with low gap fill aspect ratio
SANDISK CORP24 citations92
US7436703B2Oct 14, 2008
Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices
SANDISK CORP21 citations92
US7362615B2Apr 22, 2008
Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices
SANDISK CORP25 citations92
US7672165B2Mar 2, 2010
Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices
SANDISK CORP1 citations48
PURAYATH VINOD ROBERT
2 patentsUS8193055B1Jun 5, 2012
Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
PURAYATH VINOD ROBERT9 citations84
US8263465B2Sep 11, 2012
Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
PURAYATH VINOD ROBERT2 citations62