Inventor

VERPLANKEN FABRICE JEAN

US103 patents

⚠️ This page may combine multiple inventors who share the name “VERPLANKEN FABRICE JEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VERPLANKEN FABRICE JEAN

IBM

Data structures for efficient processing of multicast transmissions

Full match (FM) search algorithm implementation for a network processor

Longest prefix match (LPM) algorithm implementation for a network processor

Data structures for efficient processing of IP fragmentation and reassembly

Controller for multiple instruction thread processors

Network processor interface for building scalable switching systems

Method and system for network processor scheduler

Cyclic redundancy check for partitioned frames

Method and system for managing congestion in a network

Network processor, memory organization and methods

Network switch using network processor and methods

Network switch and components and method of operation

Full match (FM) search algorithm implementation for a network processor

Network processor which makes thread execution control decisions based on latency event lengths

Network switch and components and method of operation

Network switch using network processor and methods

Network processor processing complex and methods

Queue manager for a buffer

Local MAC address learning in layer 2 frame forwarding

Scheduler, network processor, and methods for weighted best effort scheduling

Method and apparatus for processing frame classification information between network processors

Stateless message processing scheme for network processors interactions

Method and system for network processor scheduling outputs using queueing

Method and system for network processor scheduling based on calculation

Storing frame modification information in a bank in memory

Network switch and components and method of operation

Host Ethernet adapter for networking offload in server environment

Longest prefix match (LPM) algorithm implementation for a network processor

High speed network processor

VLSI network processor and methods

Network switch using network processor and methods

Data transfer system for multiple network processors using dual DRAM storage

Integrated physical coding sublayer and forward error correction in networking applications

Controller for multiple instruction thread processors

Network communications for operating system partitions

Method and system for network processor scheduling based on service levels

Method and system for data flow multicasting

Method and system for network processor scheduling outputs based on multiple calendars

Method and system for network data flow management with improved completion unit

Network processor probing and port mirroring

STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports

Method and apparatus for transmission on a 2-bit channel using 3b/4b code

Longest prefix match (LPM) algorithm implementation for a network processor

Network switch and components and method of operation

System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position

Sequence-preserving deep-packet processing in a multiprocessor system

Method and system for network processor scheduling outputs using disconnect/reconnect flow queues

Method and system for making a frame alteration in a network processing system

BASSO CLAUDE

Apparatus for blind checksum and correction for network transmissions

CALVIGNAC JEAN LOUIS

Hybrid search memory for network processor and computer systems