Inventor

BOBBA SUDHAKAR

US34 patents

⚠️ This page may combine multiple inventors who share the name “BOBBA SUDHAKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOBBA SUDHAKAR

SUN MICROSYSTEMS INC

Duty cycle corrector

Clock power reduction technique using multi-level voltage input clock driver

Programmable current source adjustment of leakage current for phase locked loop

Noise immune transmission gate

Clock skew reduction using active shields

Current crowding reduction technique for flip chip package technology

Region-based voltage drop budgets for low-power design

Dynamic modulation of on-chip supply voltage for low-power design

Shield assignment using preferential shields

Multiple supply voltage dynamic logic

Decoupling capacitor assignment technique with respect to leakage power

Signal routing based approach for increasing decoupling capacitance using preferential shielding

Sliding grid based technique for optimal on-chip decap insertion

Phase locked loop design with switch for loop filter capacitance leakage current control

Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid

Phase locked loop design with diode for loop filter capacitance leakage current control

Transmission gate based signal transition accelerator

Decoupling capacitance assignment technique with minimum leakage power

Technique for optimizing decoupling capacitance subject to leakage power constraints

Increasing implicit decoupling capacitance using asymmetric shieldings

Increasing decoupling capacitance using preferential shields

180 degree bump placement layout for an integrated circuit power grid

Signal shielding assignment technique for precharge based logic

90 degree bump placement layout for an integrated circuit power grid

60 degree bump placement layout for an integrated circuit power grid

Accuracy of timing analysis using region-based voltage drop budgets

Frequency multiplier design

Thin capacitive structure

Signal shielding technique using active shields for non-interacting driver design

150 degree bump placement layout for an integrated circuit power grid

Logic optimization for preferential shields

120 degree bump placement layout for an integrated circuit power grid

KONSTADINIDIS GEORGIOS

Microprocessor performance and power optimization through self calibrated inductive voltage droop monitoring and correction

KONSTADINIDIS GEORGIOS K

Microprocessor performance and power optimization through inductive voltage droop monitoring and correction