Inventor

TRIVEDI PRADEEP

US47 patents

⚠️ This page may combine multiple inventors who share the name “TRIVEDI PRADEEP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRIVEDI PRADEEP

SUN MICROSYSTEMS INC

Dual-edge triggered dynamic logic

Duty cycle corrector

Quantifying a difference between nodal voltages

Method for optimizing loop bandwidth in delay locked loops

Clock power reduction technique using multi-level voltage input clock driver

Programmable bias-generator for self-biasing a delay locked loop

Noise immune transmission gate

Method and apparatus to store delay locked loop biasing parameters

Jitter estimation for a phase locked loop

Method for decoupling capacitor optimization for a temperature sensor design

Optimization of loop bandwidth for a phase locked loop

Circuit for post-silicon control of delay locked loop charge pump current

Calibration technique for delay locked loop leakage current

Delay locked loop design with switch for loop filter capacitance leakage current control

Current crowding reduction technique for flip chip package technology

Region-based voltage drop budgets for low-power design

Clock detect indicator

Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor

Method and apparatus for calibrating a delay locked loop charge pump current

Post-silicon phase offset control of phase locked loop input receiver

Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump

Dynamic modulation of on-chip supply voltage for low-power design

Delay locked loop design with diode for loop filter capacitance leakage current control

Method and system for estimating jitter in a delay locked loop

Post-silicon control of phase locked loop charge pump current

Multiple supply voltage dynamic logic

Decoupling capacitor assignment technique with respect to leakage power

Sliding grid based technique for optimal on-chip decap insertion

Phase locked loop design with switch for loop filter capacitance leakage current control

Post-silicon control of an embedded temperature sensor

Adjustment and calibration system for post-fabrication treatment of on-chip temperature sensor

Self-correcting I/O interface driver scheme for memory interface

Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver

System and method for in-situ signal delay measurement for a microprocessor

Phase locked loop design with diode for loop filter capacitance leakage current control

Transmission gate based signal transition accelerator

Phase locked loop input receiver design with delay matching feature

Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop

Method for simulating power supply noise in an on-chip temperature sensor

Technique for optimizing decoupling capacitance subject to leakage power constraints

Post-silicon bias-generator control for a differential phase locked loop

180 degree bump placement layout for an integrated circuit power grid

Accuracy of timing analysis using region-based voltage drop budgets

Frequency multiplier design

Calibration technique for phase locked loop leakage current

150 degree bump placement layout for an integrated circuit power grid

APPLE INC

Digital on-chip duty cycle monitoring device