Inventor

HOOPER DONALD F

US60 patents

⚠️ This page may combine multiple inventors who share the name “HOOPER DONALD F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOOPER DONALD F

INTEL CORP

Microengine for parallel processor architecture

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Register set used in multithreaded parallel processor architecture

Allocation of packets and threads

Graphical user interface that displays operation of processor threads over time

Longest prefix match for IP routers

Multi-threaded sequenced receive for fast network port stream of packets

Multi-threaded sequenced transmit software for packet forwarding device

Breakpoint method for parallel hardware threads in multithreaded processor

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Multi-threaded round-robin receive for fast network port

Multi-threaded sequenced receive for fast network port stream of packets

Network packet processing

Microengine for parallel processor architecture

Queue management

Processing a network packet using queues

Distributed lookup based on packet contents

Transmitting multicast data packets

Method for memory allocation and management using push/pop apparatus

Graphical user interface for use during processor simulation

Processing a data packet

Flow control in a network environment

Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method

Method and apparatus for performing cyclic redundancy checks

Hop method for stepping parallel hardware threads

DSL transmit traffic shaper structure and procedure

Multiple calendar schedule reservation structure and method

Register set used in multithreaded parallel processor architecture

Branch instruction for processor with branching dependent on a specified bit in a register

Instruction operand tracing for software debug

Folding for a multi-threaded network processor

Graphical user interface

Circular link list scheduling

Multiple image dynamic bind and load procedure for a multi-processor

Network multicasting

Method and apparatus to support a large internet protocol forwarding information base

DIGITAL EQUIPMENT CORP

Video on demand with memory accessing and or like functions

Segmented video on demand system

Distributed interactive multimedia service system

Remote display of an image by transmitting compressed video frames representing back-ground and overlay portions thereof

Remote display of an image by transmitting compressed video frames representing background and overlay portions thereof

Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design

Bitwise implementation mechanism for a circuit design synthesis procedure

Procedure and data structure for synthesis and transformation of logic circuit designs

Rule structure in a procedure for synthesis of logic circuits

Procedure for incorporating timing parameters in the synthesis of logic circuit designs

Rule structure for insertion of new elements in a circuit design synthesis procedure

Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs

Database generator

Groups of tag signals for data store in multi-plane set of buffers