Inventor

JENG PEI-REN

TW98 patents

⚠️ This page may combine multiple inventors who share the name “JENG PEI-REN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JENG PEI-REN

MACRONIX INT CO LTD

Method for planarizing a flash memory device

Method of improving the interlayer adhesion property of low-k layers in a dual damascene process

Method for preventing polysilicon stringer in memory device

Method for barrier layer in copper manufacture

Method for forming shallow trench isolation

Method of fabricating self-aligned multilevel mask ROM

Method of forming shallow trench isolation

Method of forming self-aligned contacts

Method of fabricating a high-coupling ratio flash memory

Method for patterning a dual damascene with masked implantation

Method for forming self-aligned mask read only memory by dual damascene trenches

Method of fabricating self-aligned multilevel mask ROM

Method for fabricating flash memory

Method for forming a high-RI oxide film to reduce fluorine diffusion in HDP FSG process

Process for a flash memory with high breakdown resistance between gate and contact

Method for forming shallow trench isolation with control of bird beak

Method for patterning a dual damascene with retrograde implantation

Method of forming a spin-on-passivation layer

High density plasma chemical vapor deposition chamber

Planarization method of memory unit of flash memory

Method of forming shallow trench isolation

Method for fabricating a dual damascene structure

Planarization method for flash memory device

TAIWAN SEMICONDUCTOR MFG CO LTD

Self aligned contact scheme

Self aligned contact scheme

FinFET with rounded source/drain profile

Selectively deposited spacer film for metal gate sidewall protection

Interfacial layer between fin and source/drain region

Apparatus and method for spatial atomic layer deposition

Method for manufacturing semiconductor structure with enlarged volumes of source-drain regions

FinFET with rounded source/drain profile

FinFET with bottom SiGe layer in source/drain

Semiconductor method and device

Self-aligned insulated film for high-k metal gate device

Apparatus and method for spatial atomic layer deposition

Protective layer over FinFET and method of forming same

In-situ straining epitaxial process

Semiconductor method and device

Semiconductor device and method

TAIWAN SEMICONDUCTOR MFG

FinFET with bottom SiGe layer in source/drain

FinFET with bottom SiGe layer in source/drain

Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio

IND TECH RES INST

Method for fabricating self-aligned double layered silicon-metal nanocrystal memory element

Interlayer interconnect of three-dimensional memory and method for manufacturing the same

Self-aligned double layered silicon-metal nanocrystal memory element, method for fabricating the same, and memory having the memory element

HOLTEK MICROELECTRONICS INC

Method for improving the electrical property of gate in polycide structure

NG JIN-AUN

Self-aligned insulated film for high-k metal gate device

JENG PEI-REN

Source/drain doping method in 3D devices

LU CHANG-SHEN

Dummy FinFET structure and method of making same

LIOU YU-LING

Uniform shallow trench isolation regions and the method of forming the same