Inventor

COL GERARD M

US69 patents

⚠️ This page may combine multiple inventors who share the name “COL GERARD M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COL GERARD M

IP FIRST LLC

Compare branch instruction pairing within a single integer pipeline

Pairing of load-ALU-store with conditional branch

Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection

Apparatus and method for branch target address calculation during instruction decode

Pop-compare micro instruction for repeat string operations

Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction

Result forwarding cache

Pairing of micro instructions in the instruction queue

Processor including fallback branch prediction mechanism for far jump and far call instructions

Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome

System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution

Paired load-branch operation for indirect near jumps

Predecode in parallel with TLB compare

Apparatus and method for improved non-page fault loads and stores

Microprocessor apparatus and method for accelerating execution of repeat string instructions

Apparatus and method for masked move to and from flags register in a processor

Address stage logic for generating speculative address operand interim results of preceding instruction by arithmetic operations and configuring

VIA ALLIANCE SEMICONDUCTOR CO LTD

Programmable load replay precluding mechanism

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Power saving mechanism to reduce load replays in out-of-order processor

Power saving mechanism to reduce load replays in out-of-order processor

Apparatus and method for programmable load replay preclusion

Apparatus and method for programmable load replay preclusion

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

Load replay precluding mechanism

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor

Load replay precluding mechanism

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor

COL GERARD M

Microprocessor with fused store address/store data microinstruction

Microprocessor with ALU integrated into load unit

Out-of-order execution microprocessor that selectively initiates instruction retirement early

Apparatus and method for masked move to and from flags register in a processor

Microprocessor with ALU integrated into store unit

Out-of-order X86 microprocessor with fast shift-by-zero handling

HENRY G GLENN

Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Conditional load instructions in an out-of-order execution microprocessor

Microprocessor with microinstruction-specifiable non-architectural condition code flag register

Conditional store instructions in an out-of-order execution microprocessor

Efficient conditional ALU instruction in read-port limited register file microprocessor

VIA TECH INC

Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture

Pipelined microprocessor, apparatus, and method for generating early instruction results

Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions

Pipelined microprocessor, apparatus, and method for generating early status flags

Processor that leapfrogs MOV instructions

I P FIRST L L C

Result forwarding cache

Update forwarding cache for address mode

HOOKER RODNEY E

Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register

Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction