Inventor

NORDSTROM GREGORY M

US41 patents

⚠️ This page may combine multiple inventors who share the name “NORDSTROM GREGORY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NORDSTROM GREGORY M

IBM

Dynamic switch protocols on a shared medium network

Implementing coherent accelerator function isolation for virtualization

Independent computer storage addressing in input/output transfers

Implementing coherent accelerator function isolation for virtualization

Cable redundancy and failover for multi-lane PCI express IO interconnections

Cable redundancy and failover for multi-lane PCI express IO interconnections

Dynamic allocation of a direct memory address window

Detecting and sparing of optical PCIE cable channel attached IO drawer

Operating PCI express resources in a logically partitioned computing system

Implementing sideband control structure for PCIE cable cards and IO expansion enclosures

Detecting and sparing of optical PCIE cable channel attached IO drawer

Detecting and configuring of external IO enclosure

Detecting and configuring of external IO enclosure

Data transfer via Host/PCI-X bridges

Implementing modal selection of bimodal coherent accelerator

Implementing modal selection of bimodal coherent accelerator

Isolation of input/output adapter error domains

Direct memory access (DMA) address translation with a consecutive count field

Direct memory access (DMA) address translation with a consecutive count field

Implementing sideband control structure for PCIE cable cards and IO expansion enclosures

Implementing sideband control structure for PCIE cable cards and IO expansion enclosures

Implementing modal selection of bimodal coherent accelerator

Implementing coherent accelerator function isolation for virtualization

Implementing coherent accelerator function isolation for virtualization

Providing virtual functions after an input/output adapter is moved from a first location to a second location

Hierarchical to physical memory mapped input/output translation

Implementing sideband control structure for PCIE cable cards and IO expansion enclosures

Detecting and sparing of optical PCIE cable channel attached IO drawer

GRAHAM CHARLES S

Managing configuration and system operations of a non-shared virtualized input/output adapter as virtual peripheral component interconnect root to single function hierarchies

Managing configuration and system operations of a shared virtualized input/output adapter as virtual peripheral component interconnect root to single function hierarchies

Managing configuration and operation of an adapter as a virtual peripheral component interconnect root to expansion read-only memory emulation

LAIS ERIC N

Implementing PCI-express memory domains for single root virtualized devices

Interrupt source controller with scalable state structures

BROWNLOW SEAN T

Enhanced error handling for self-virtualizing input/output device in logically-partitioned data processing system

Address translation table to enable access to virtualized functions

BUCKLAND PATRICK A

Cable redundancy and failover for multi-lane PCI express IO interconnections

Cable redundancy and failover for multi-lane PCI express IO interconnections

ARMSTRONG WILLIAM J

Hierarchical to physical bus translation

Physical to hierarchical bus translation

HARADEN RYAN S

Method for correlating an error message from a PCI express endpoint

NORDSTROM GREGORY M

Memory mapped input/output bus address range translation for virtual bridges