Inventor
EDIRISOORIYA SAMANTHA J
US36 patents
⚠️ This page may combine multiple inventors who share the name “EDIRISOORIYA SAMANTHA J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS6775748B2Aug 10, 2004
Methods and apparatus for transferring cache block ownership
INTEL CORP20 citations92
US7343546B2Mar 11, 2008
Method and system for syndrome generation and data recovery
INTEL CORP16 citations90
US7404043B2Jul 22, 2008
Cache memory to support a processor's power mode of operation
INTEL CORP11 citations84
US7159077B2Jan 2, 2007
Direct processor cache access within a system having a coherent multi-processor protocol
INTEL CORP16 citations84
US7100001B2Aug 29, 2006
Methods and apparatus for cache intervention
INTEL CORP16 citations84
US10241947B2Mar 26, 2019
Hardware-based virtual machine communication
INTEL CORP6 citations83
US7290093B2Oct 30, 2007
Cache memory to support a processor's power mode of operation
INTEL CORP5 citations74
US7143220B2Nov 28, 2006
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
INTEL CORP6 citations74
US7062613B2Jun 13, 2006
Methods and apparatus for cache intervention
INTEL CORP5 citations74
US6983348B2Jan 3, 2006
Methods and apparatus for cache intervention
INTEL CORP10 citations74
US9953001B2Apr 24, 2018
Method, apparatus, and system for plugin mechanism of computer extension bus
INTEL CORP2 citations70
US10127968B2Nov 13, 2018
Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode
INTEL CORP3 citations66
US7464227B2Dec 9, 2008
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
INTEL CORP6 citations63
US7447810B2Nov 4, 2008
Implementing bufferless Direct Memory Access (DMA) controllers using split transactions
INTEL CORP4 citations63
US7330998B2Feb 12, 2008
Data integrity verification
INTEL CORP4 citations63
US7234028B2Jun 19, 2007
Power/performance optimized cache using memory write prevention through write snarfing
INTEL CORP3 citations63
US10990546B2Apr 27, 2021
Hardware-based virtual machine communication supporting direct memory access data transfer
INTEL CORP0 citations61
US7757046B2Jul 13, 2010
Method and apparatus for optimizing line writes in cache coherent systems
INTEL CORP0 citations52
US7698476B2Apr 13, 2010
Implementing bufferless direct memory access (DMA) controllers using split transactions
INTEL CORP0 citations52
US7685379B2Mar 23, 2010
Cache memory to support a processor's power mode of operation
INTEL CORP0 citations52
US7487299B2Feb 3, 2009
Cache memory to support a processor's power mode of operation
INTEL CORP0 citations52
US7360007B2Apr 15, 2008
System including a segmentable, shared bus
INTEL CORP1 citations52
US10235302B2Mar 19, 2019
Invalidating reads for cache utilization in processors
INTEL CORP0 citations51
US7640387B2Dec 29, 2009
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP0 citations51
US7353317B2Apr 1, 2008
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP1 citations51
US10679690B2Jun 9, 2020
Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode
INTEL CORP0 citations45
MARVELL INT LTD
8 patentsUS7406553B2Jul 29, 2008
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD18 citations92
US7634603B2Dec 15, 2009
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD4 citations74
US7428607B2Sep 23, 2008
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD5 citations74
US7219176B2May 15, 2007
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD6 citations74
US7966477B1Jun 21, 2011
Power optimized replay of blocked operations in a pipilined architecture
MARVELL INT LTD0 citations52
US7765349B1Jul 27, 2010
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD0 citations52
US7725683B2May 25, 2010
Apparatus and method for power optimized replay via selective recirculation of instructions
MARVELL INT LTD0 citations52
US7406552B2Jul 29, 2008
Systems and methods for early fixed latency subtractive decoding including speculative acknowledging
MARVELL INT LTD0 citations52