Inventor

JAMIL SUJAT

US67 patents

⚠️ This page may combine multiple inventors who share the name “JAMIL SUJAT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAMIL SUJAT

INTEL CORP

System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions

On-die mechanism for high-reliability processor

Method and apparatus for preventing and recovering from TLB corruption by soft error

Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions

Methods and apparatus for transferring cache block ownership

System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors

Method and apparatus for scalable disambiguated coherence in shared storage hierarchies

Silent data corruption prevention due to instruction corruption by soft errors

Transfer of cache lines on-chip between processing cores in a multi-core system

Method and apparatus for preventing and recovering from TLB corruption by soft error

Cache memory to support a processor&#39;s power mode of operation

Direct processor cache access within a system having a coherent multi-processor protocol

Methods and apparatus for cache intervention

Mechanism handling race conditions in FRC-enabled processors

Method and apparatus for scalable disambiguated coherence in shared storage hierarchies

Cache memory to support a processor&#39;s power mode of operation

Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies

Methods and apparatus for cache intervention

Methods and apparatus for cache intervention

Method and apparatus for supporting opportunistic sharing in coherent multiprocessors

Power/performance optimized cache using memory write prevention through write snarfing

Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput

MARVELL INT LTD

Thread-aware cache memory management

Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache

System and apparatus for early fixed latency subtractive decoding

Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses

Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture

System and apparatus for early fixed latency subtractive decoding

Apparatus and method for arbitrating heterogeneous agents in on-chip busses

System and apparatus for early fixed latency subtractive decoding

Method and apparatus for processing speculative, out-of-order memory access instructions

Managing aliasing in a virtually indexed physically tagged cache

Method and apparatus for associating requests and responses with identification information

Programmable cache access protocol to optimize power consumption and performance

Power optimized replay of blocked operations in a pipilined architecture

O'BLENESS R FRANK

Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison

Way-selecting translation lookaside buffer

Dynamic pipeline reconfiguration including changing a number of stages

Method and apparatus for hardware-configurable multi-policy coherence protocol

JAMIL SUJAT

Cache memory bank selection

Detecting and reissuing of loop instructions in reorder structure

Method and apparatus for improving cache efficiency

QUALCOMM INC

Method and system for variable thread allocation and switching in a multithreaded processor

Processor and method of grouping and executing dependent instructions in a packet

Low power microprocessor cache memory and method of operation

DELGROSS JOSEPH

Programmable cache access protocol to optimize power consumption and performance

EDIRISOORIYA SAMANTHA J

Implementing direct access caches in coherent multiprocessors

O'BLENESS FRANK

Method and apparatus for data-less bus query

SCHUTTENBERG KIM

Systems and methods for reducing interrupt latency

BASSETT PAUL DOUGLAS

Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode

Cache memory to support a processor's power mode of operation

Cache memory to support a processor's power mode of operation