Inventor
O'BLENESS R FRANK
US47 patents
⚠️ This page may combine multiple inventors who share the name “O'BLENESS R FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARVELL INT LTD
17 patentsUS9223709B1Dec 29, 2015
Thread-aware cache memory management
MARVELL INT LTD49 citations94
US9934152B1Apr 3, 2018
Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache
MARVELL INT LTD24 citations93
US7406553B2Jul 29, 2008
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD18 citations92
US9606800B1Mar 28, 2017
Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture
MARVELL INT LTD9 citations84
US9141543B1Sep 22, 2015
Systems and methods for writing data from a caching agent to main memory according to a pre-clean criterion
MARVELL INT LTD12 citations83
US7634603B2Dec 15, 2009
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD4 citations74
US7428607B2Sep 23, 2008
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD5 citations74
US7219176B2May 15, 2007
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD6 citations74
US9442735B1Sep 13, 2016
Method and apparatus for processing speculative, out-of-order memory access instructions
MARVELL INT LTD6 citations73
US9842051B1Dec 12, 2017
Managing aliasing in a virtually indexed physically tagged cache
MARVELL INT LTD4 citations72
US8688919B1Apr 1, 2014
Method and apparatus for associating requests and responses with identification information
MARVELL INT LTD2 citations62
US8769204B1Jul 1, 2014
Programmable cache access protocol to optimize power consumption and performance
MARVELL INT LTD0 citations52
US7966477B1Jun 21, 2011
Power optimized replay of blocked operations in a pipilined architecture
MARVELL INT LTD0 citations52
US7765349B1Jul 27, 2010
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD0 citations52
US7725683B2May 25, 2010
Apparatus and method for power optimized replay via selective recirculation of instructions
MARVELL INT LTD0 citations52
US7406552B2Jul 29, 2008
Systems and methods for early fixed latency subtractive decoding including speculative acknowledging
MARVELL INT LTD0 citations52
US9086976B1Jul 21, 2015
Method and apparatus for associating requests and responses with identification information
MARVELL INT LTD0 citations51
INTEL CORP
17 patentsUS6775748B2Aug 10, 2004
Methods and apparatus for transferring cache block ownership
INTEL CORP20 citations92
US7404043B2Jul 22, 2008
Cache memory to support a processor's power mode of operation
INTEL CORP11 citations84
US7159077B2Jan 2, 2007
Direct processor cache access within a system having a coherent multi-processor protocol
INTEL CORP16 citations84
US7100001B2Aug 29, 2006
Methods and apparatus for cache intervention
INTEL CORP16 citations84
US7290093B2Oct 30, 2007
Cache memory to support a processor's power mode of operation
INTEL CORP5 citations74
US7143220B2Nov 28, 2006
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
INTEL CORP6 citations74
US7062613B2Jun 13, 2006
Methods and apparatus for cache intervention
INTEL CORP5 citations74
US6983348B2Jan 3, 2006
Methods and apparatus for cache intervention
INTEL CORP10 citations74
US7464227B2Dec 9, 2008
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
INTEL CORP6 citations63
US7234028B2Jun 19, 2007
Power/performance optimized cache using memory write prevention through write snarfing
INTEL CORP3 citations63
US7694080B2Apr 6, 2010
Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput
INTEL CORP3 citations62
US7757046B2Jul 13, 2010
Method and apparatus for optimizing line writes in cache coherent systems
INTEL CORP0 citations52
US7685379B2Mar 23, 2010
Cache memory to support a processor's power mode of operation
INTEL CORP0 citations52
US7487299B2Feb 3, 2009
Cache memory to support a processor's power mode of operation
INTEL CORP0 citations52
US7640387B2Dec 29, 2009
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP0 citations51
US7353317B2Apr 1, 2008
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP1 citations51
US7366845B2Apr 29, 2008
Pushing of clean data to one or more processors in a system having a coherency protocol
INTEL CORP1 citations50
O'BLENESS R FRANK
4 patentsUS8918625B1Dec 23, 2014
Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison
O'BLENESS R FRANK59 citations97
US8631206B1Jan 14, 2014
Way-selecting translation lookaside buffer
O'BLENESS R FRANK11 citations83
US8806181B1Aug 12, 2014
Dynamic pipeline reconfiguration including changing a number of stages
O'BLENESS R FRANK14 citations82
US8135916B1Mar 13, 2012
Method and apparatus for hardware-configurable multi-policy coherence protocol
O'BLENESS R FRANK19 citations82