Inventor
TU STEVEN J
US36 patents
⚠️ This page may combine multiple inventors who share the name “TU STEVEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
25 patentsUS7055060B2May 30, 2006
On-die mechanism for high-reliability processor
INTEL CORP85 citations96
US6954886B2Oct 11, 2005
Deterministic hardware reset for FRC machine
INTEL CORP22 citations92
US6775748B2Aug 10, 2004
Methods and apparatus for transferring cache block ownership
INTEL CORP20 citations92
US7139947B2Nov 21, 2006
Test access port
INTEL CORP20 citations91
US7404043B2Jul 22, 2008
Cache memory to support a processor's power mode of operation
INTEL CORP11 citations84
US7159077B2Jan 2, 2007
Direct processor cache access within a system having a coherent multi-processor protocol
INTEL CORP16 citations84
US7100001B2Aug 29, 2006
Methods and apparatus for cache intervention
INTEL CORP16 citations84
US6412062B1Jun 25, 2002
Injection control mechanism for external events
INTEL CORP16 citations84
US7627797B2Dec 1, 2009
Test access port
INTEL CORP8 citations83
US7194671B2Mar 20, 2007
Mechanism handling race conditions in FRC-enabled processors
INTEL CORP14 citations82
US7290093B2Oct 30, 2007
Cache memory to support a processor's power mode of operation
INTEL CORP5 citations74
US7143220B2Nov 28, 2006
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
INTEL CORP6 citations74
US7062613B2Jun 13, 2006
Methods and apparatus for cache intervention
INTEL CORP5 citations74
US6983348B2Jan 3, 2006
Methods and apparatus for cache intervention
INTEL CORP10 citations74
US7944502B2May 17, 2011
Pipelining techniques for deinterlacing video information
INTEL CORP5 citations69
US7464227B2Dec 9, 2008
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
INTEL CORP6 citations63
US7234028B2Jun 19, 2007
Power/performance optimized cache using memory write prevention through write snarfing
INTEL CORP3 citations63
US7757046B2Jul 13, 2010
Method and apparatus for optimizing line writes in cache coherent systems
INTEL CORP0 citations52
US7685379B2Mar 23, 2010
Cache memory to support a processor's power mode of operation
INTEL CORP0 citations52
US7487299B2Feb 3, 2009
Cache memory to support a processor's power mode of operation
INTEL CORP0 citations52
US7640387B2Dec 29, 2009
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP0 citations51
US7353317B2Apr 1, 2008
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP1 citations51
US7366845B2Apr 29, 2008
Pushing of clean data to one or more processors in a system having a coherency protocol
INTEL CORP1 citations50
US7952643B2May 31, 2011
Pipelining techniques for deinterlacing video information
INTEL CORP0 citations48
US7804542B2Sep 28, 2010
Spatio-temporal adaptive video de-interlacing for parallel processing
INTEL CORP0 citations39
MARVELL INT LTD
8 patentsUS7406553B2Jul 29, 2008
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD18 citations92
US7634603B2Dec 15, 2009
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD4 citations74
US7428607B2Sep 23, 2008
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD5 citations74
US7219176B2May 15, 2007
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD6 citations74
US7966477B1Jun 21, 2011
Power optimized replay of blocked operations in a pipilined architecture
MARVELL INT LTD0 citations52
US7765349B1Jul 27, 2010
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD0 citations52
US7725683B2May 25, 2010
Apparatus and method for power optimized replay via selective recirculation of instructions
MARVELL INT LTD0 citations52
US7406552B2Jul 29, 2008
Systems and methods for early fixed latency subtractive decoding including speculative acknowledging
MARVELL INT LTD0 citations52