Inventor
NGUYEN HANG T
US41 patents
⚠️ This page may combine multiple inventors who share the name “NGUYEN HANG T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS6564332B1May 13, 2003
Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet
INTEL CORP92 citations98
US7055060B2May 30, 2006
On-die mechanism for high-reliability processor
INTEL CORP85 citations96
US6954886B2Oct 11, 2005
Deterministic hardware reset for FRC machine
INTEL CORP22 citations92
US6658621B1Dec 2, 2003
System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors
INTEL CORP27 citations91
US6543028B1Apr 1, 2003
Silent data corruption prevention due to instruction corruption by soft errors
INTEL CORP50 citations91
US8375184B2Feb 12, 2013
Mirroring data between redundant storage controllers of a storage system
INTEL CORP24 citations89
US7159077B2Jan 2, 2007
Direct processor cache access within a system having a coherent multi-processor protocol
INTEL CORP16 citations84
US7100001B2Aug 29, 2006
Methods and apparatus for cache intervention
INTEL CORP16 citations84
US9032226B2May 12, 2015
Providing per core voltage and frequency control
INTEL CORP8 citations83
US7194671B2Mar 20, 2007
Mechanism handling race conditions in FRC-enabled processors
INTEL CORP14 citations82
US7143220B2Nov 28, 2006
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
INTEL CORP6 citations74
US7062613B2Jun 13, 2006
Methods and apparatus for cache intervention
INTEL CORP5 citations74
US10936449B2Mar 2, 2021
Component redundancy systems, devices, and methods
INTEL CORP2 citations72
US10613620B2Apr 7, 2020
Providing per core voltage and frequency control
INTEL CORP1 citations72
US10345884B2Jul 9, 2019
Mechanism to provide workload and configuration-aware deterministic performance for microprocessors
INTEL CORP2 citations71
US7464227B2Dec 9, 2008
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
INTEL CORP6 citations63
US9983661B2May 29, 2018
Providing per core voltage and frequency control
INTEL CORP1 citations62
US7694080B2Apr 6, 2010
Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput
INTEL CORP3 citations62
US7757046B2Jul 13, 2010
Method and apparatus for optimizing line writes in cache coherent systems
INTEL CORP0 citations52
US7360007B2Apr 15, 2008
System including a segmentable, shared bus
INTEL CORP1 citations52
US9992299B2Jun 5, 2018
Technologies for network packet cache management
INTEL CORP0 citations51
US9983659B2May 29, 2018
Providing per core voltage and frequency control
INTEL CORP0 citations51
US9983660B2May 29, 2018
Providing per core voltage and frequency control
INTEL CORP0 citations51
US9939884B2Apr 10, 2018
Providing per core voltage and frequency control
INTEL CORP0 citations51
US9866498B2Jan 9, 2018
Technologies for network packet cache management
INTEL CORP0 citations51
US9348387B2May 24, 2016
Providing per core voltage and frequency control
INTEL CORP0 citations51
US7640387B2Dec 29, 2009
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP0 citations51
US7353317B2Apr 1, 2008
Method and apparatus for implementing heterogeneous interconnects
INTEL CORP1 citations51
US9417681B2Aug 16, 2016
Mechanism to provide workload and configuration-aware deterministic performance for microprocessors
INTEL CORP0 citations50
US7366845B2Apr 29, 2008
Pushing of clean data to one or more processors in a system having a coherency protocol
INTEL CORP1 citations50
MARVELL INT LTD
6 patentsUS7406553B2Jul 29, 2008
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD18 citations92
US7634603B2Dec 15, 2009
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD4 citations74
US7428607B2Sep 23, 2008
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD5 citations74
US7219176B2May 15, 2007
System and apparatus for early fixed latency subtractive decoding
MARVELL INT LTD6 citations74
US7765349B1Jul 27, 2010
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
MARVELL INT LTD0 citations52
US7406552B2Jul 29, 2008
Systems and methods for early fixed latency subtractive decoding including speculative acknowledging
MARVELL INT LTD0 citations52