Inventor

CHANDA KAUSHIK

US54 patents

⚠️ This page may combine multiple inventors who share the name “CHANDA KAUSHIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANDA KAUSHIK

IBM

Structure and method for monitoring stress-induced degradation of conductive interconnects

Interconnect structure with bi-layer metal cap

Metal resistor, resistor material and method

Interconnect structure for integrated circuits having improved electromigration characteristics

E-fuse structures and methods of manufacture

Method for fabricating air gap interconnect structures

Addressable hierarchical metal wire test methodology

Structure and method of forming electrically blown metal fuses for integrated circuits

Method of forming an interconnect including a dielectric cap having a tensile stress

Semiconductor wiring structures including dielectric cap within metal cap layer

Back-end electrically programmable fuse

Interconnect structure with enhanced reliability

Via bottom contact and method of manufacturing same

Stacked via structure for metal fuse applications

Electrically programmable fuse and fabrication method

Reliability of wide interconnects

Test structure for electromigration analysis and related method

Test structure for electromigration analysis and related method

Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing

Method for prediction of premature dielectric breakdown in a semiconductor

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

Structure for monitoring stress-induced degradation of conductive interconnects

VIA bottom contact and method of manufacturing same

Hybrid metallic wire and methods of fabricating same

Stacked via structure for metal fuse applications

Stacked via structure for metal fuse applications

Methods and systems involving electrically reprogrammable fuses

Electrically programmable fuse and fabrication method

Metal resistor and resistor material

Structure for modeling stress-induced degradation of conductive interconnects

BONILLA GRISELDA

Metal fuse structure for improved programming capability

Interconnect structure for integrated circuits having enhanced electromigration resistance

Capping of copper interconnect lines in integrated circuit devices

Fuse and integrated conductor

E-fuse structures and methods of manufacture

CHANDA KAUSHIK

Air gap interconnect structures and methods for forming the same

Stress locking layer for reliable metallization

Methods and systems involving electrically reprogrammable fuses

YANG CHIH-CHAO

Interconnect structures, design structure and method of manufacture

Metal cap for back end of line (BEOL) interconnects, design structure and method of manufacture

Method of manufacturing an interconnect structure and design structure thereof

ALTERA CORP

Power line layout in integrated circuits

Methods and apparatus for automated integrated circuit package testing

FILIPPI RONALD G

Stacked via structure for metal fuse applications

INFINEON TECHNOLOGIES CORP

Simultaneous native oxide removal and metal neutral deposition method

BAO JUNJING

Back-end electrically programmable fuse

GLOBALFOUNDRIES INC

Metal fuse structure for improved programming capability

RENSSELAER POLYTECH INST

Diffusion barriers comprising a self-assembled monolayer

FILIPPI RONALD

Interconnect structure with enhanced reliability

INTEL CORP

Systems and methods for circuit design dependent programmable maximum junction temperatures