Inventor

GREGG THOMAS A

US164 patents

⚠️ This page may combine multiple inventors who share the name “GREGG THOMAS A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GREGG THOMAS A

IBM

I/O adapter LPAR isolation with assigned memory space

Memory mapped Input/Output operations

System of controlling the flow of information between senders and receivers across links being used as channels

Multi channel inter-processor coupling facility processing received commands stored in memory absent status error of channels

Suspending, resuming, and interleaving frame-groups

Method for transferring data between processors on a network by establishing an address space for each processor in each other processor&#39;s

Recovery of lost frames in a communication link

Low latency multicast for infiniband® host channel adapters

Method, system, and apparatus for accelerating resolution of network congestion

Method, system, and computer program product for adaptive congestion control on virtual lanes for data center ethernet architecture

I/O adapter LPAR isolation in a hypertransport environment

Transparent PCI-based multi-host switch

Long distance repeater for digital information

Employing a data mover to communicate between dynamically selected zones of a central processing complex

System for high speed transfer of data frames between a channel and an input/output device with request and backup request count registers

Apparatus for decoding frames from a data link

Data synchronizing buffers for data processing channels

Byte count handling in serial channel extender with buffering for data pre-fetch

Event queue in a logical partition

Low latency send queues in I/O adapter hardware

System and method for providing multiple virtual host channel adapters using virtual switches

Memory mapped input/output virtualization

Event queue in a logical partition

Event queue structure and method

Memory mapped input/output emulation

Method of controlling the flow of information between senders and receivers across links being used as channels

Facility for intializing a fiber optic data link in one mode of a plurality of modes

System for identifying communication sequences transmitted across multiple carriers by examining bit streams for sequences of valid words

Self-timed parallel inter-system data communication channel

Null words for pacing serial links to driver and receiver speeds

Configurable, recoverable parallel bus

Frame group transmission and reception for parallel/serial buses

Skew measurement for receiving frame-groups

Communications system having plurality of originator and corresponding recipient buffers with each buffer having three different logical areas for transmitting messages in single transfer

Configurable, recoverable parallel bus

Apparatus for constructing data frames for transmission over a data link

Shortened timeout period during frame retry in a communication link

Maintaining information from a damaged frame by the receiver in a communication link

I/O operation-level error checking

Store peripheral component interconnect (PCI) function controls instruction

CRADDOCK DAVID

Controlling access by a configuration to an adapter function

Translation of input/output addresses to memory addresses

Controlling the selectively setting of operational parameters for an adapter

Delaying acknowledgment of an operation until operation completion confirmed by local adapter read operation

CHECK MARK A

Memory error isolation and recovery in a multiprocessor computer system

KRISHNAMURTHY RAJARAM B

Managing task execution on accelerators

(unassigned)

Error detection and recovery in parallel/serial buses

CONESKI ANTHONY F

Managing processing associated with hardware events

BAYER GERD K

Switch failover control in a multiprocessor computer system

LAIS ERIC N

System and method for routing I/O expansion requests and responses in a PCIE architecture

Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's