Inventor

OSISEK DAMIAN L

US149 patents

⚠️ This page may combine multiple inventors who share the name “OSISEK DAMIAN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OSISEK DAMIAN L

IBM

Allocation of address spaces within virtual machine compute system

Interpreting I/O operation requests from pageable guests without host intervention

Computer system which supports asynchronous commitment of data

Use of test protection instruction in computing environments that support pageable guests

Managing input/output interruptions in non-dedicated interruption hardware environments, and methods therefor

Managing input/output interruptions in non-dedicated interruption hardware environments

Method and apparatus for managing the execution of a broadcast instruction on a guest processor

Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system

Program event recording within a transactional environment

Execution of a perform frame management function instruction

Emulating execution of a perform frame management instruction

Use of test protection instruction in computing environments that support pageable guests

Method, system and computer program product for providing filtering of GUEST2 quiesce requests

Load page table entry address instruction execution based on an address translation format control field

Facilitating processing within computing environments supporting pageable guests

Central processing unit measurement facility

Memory mapped input/output virtualization

Managing input/output interruptions in non-dedicated interruption hardware environments

Passive serialization in a multitasking environment

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Creating a dynamic address translation with translation exception qualifiers

Set buffer state instruction

Creating a dynamic address translation with translation exception qualifiers

Address expansion and contraction in a multithreading computer system

Thread context preservation in a multithreading computer system

Managing storage protection faults

Managing storage protection faults

Dynamic enablement of multithreading

Performing a clear operation absent host intervention

Use of test protection instruction in computing environments that support pageable guests

Creating a dynamic address translation with translation exception qualifier

Use of test protection instruction in computing environments that support pageable guests

Set sampling controls instruction

Execution of a perform frame management function instruction

GREINER DAN F

Program event recording within a transactional environment

Perform frame management function instruction for setting storage keys and clearing blocks of main storage

Dynamic address translation with frame management

Dynamic address translation with change record override

Dynamic address translation with translation table entry format control for indentifying format of the translation table entry

Load page table entry address instruction execution based on an address translation format control field

Dynamic address translation with translation exception qualifier

GAINEY JR CHARLES W

Optimizations of a perform frame management function issued by pageable guests

Execution of a perform frame management function instruction

Clearing guest frames absent paging-in to host main storage

FARRELL MARK S

Managing use of storage by multiple pageable guests of a computing environment

Use of test protection instruction in computing environments that support pageable guests

BARTIK JANE H

Query sampling information instruction

Set sampling controls instruction

EASTON JANET R

Interpreting I/O operation requests from pageable guests without host intervention

Interpreting I/O operation requests from pageable guests without host intervention