Inventor

MALHOTRA SANDRA G

US76 patents

⚠️ This page may combine multiple inventors who share the name “MALHOTRA SANDRA G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MALHOTRA SANDRA G

INTERMOLECULAR INC

Enhanced non-noble electrode layers for DRAM capacitor cell

Methods for forming resistive-switching metal oxides for nonvolatile memory elements

DRAM MIM capacitor using non-noble electrodes

Methods for reproducible flash layer deposition

Methods for reproducible flash layer deposition

DRAM MIM capacitor using non-noble electrodes

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

High performance dielectric stack for DRAM capacitor

Methods for forming resistive-switching metal oxides for nonvolatile memory elements

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Methods for forming resistive-switching metal oxides for nonvolatile memory elements

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Substrate processing including a masking layer

Titanium based high-K dielectric films

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Resistive-switching nonvolatile memory elements

Methods of combinatorial processing for screening multiple samples on a semiconductor substrate

Semiconductor stacks including catalytic layers

Substrate processing including a masking layer

Blocking layers for leakage current reduction in DRAM devices

Blocking layers for leakage current reduction in DRAM devices

Top electrode templating for DRAM capacitor

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric regions

IBM

Method of forming barrier layers for damascene interconnects

Dual etch stop/diffusion barrier for damascene interconnects

Copper recess process with application to selective capping and electroless plating

Method for increasing deposition rates of metal layers from metal-carbonyl precursors

Structure and method of forming electrodeposited contacts

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

Copper recess process with application to selective capping and electroless plating

Low-pressure deposition of metal layers from metal-carbonyl precursors

Method for electroplating on resistive substrates

Method for depositing a metal layer on a semiconductor interconnect structure

Copper seed layer repair technique using electroless touch-up

Method of forming a metal layer using an intermittent precursor gas flow process

Method of forming electrodeposited contacts

Method of depositing metal layers from metal-carbonyl precursors

Process for fabricating a semiconductor structure having a self-aligned spacer

MALHOTRA SANDRA G

Nonvolatile memory element including resistive switching metal oxide layers

Integration of non-noble DRAM electrode

LAZOVSKY DAVID E

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

CHEN HANHONG

Methods for forming high-K crystalline films and related devices

Enhanced non-noble electrode layers for DRAM capacitor cell

KUMAR PRAGATI

Resistive-switching nonvolatile memory elements

CABRAL JR CYRIL

Contact metallurgy structure

TOKYO ELECTRON LTD

Method for preparing solid precursor tray for use in solid precursor evaporation system

CHIANG TONY P

Leakage reduction in DRAM MIM capacitors