Inventor

WU YIDER

US60 patents

⚠️ This page may combine multiple inventors who share the name “WU YIDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU YIDER

ADVANCED MICRO DEVICES INC

Flash memory erase speed by fluorine implant or fluorination

Multi-bit silicon nitride charge-trapping non-volatile memory cell

Die seal for semiconductor device moisture protection

Erase method for dual bit virtual ground flash

Method of simultaneous formation of bitline isolation and periphery oxide

Source drain implant during ONO formation for improved isolation of SONOS devices

Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory

Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory

Simultaneous formation of charge storage and bitline to wordline isolation

Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device

Simultaneous formation of charge storage and bitline to wordline isolation

Data retention characteristics as a result of high temperature bake

Non-volatile memory device

Non-volatile memory device

Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space

Method and structure for protecting NROM devices from induced charge damage during device fabrication

Methods for fabricating and planarizing dual poly scalable SONOS flash memory

Structure and method for suppressing oxide encroachment in a floating gate memory cell

Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory

Method of forming ONO flash memory devices using low energy nitrogen implantation

Memory circuit for suppressing bit line current leakage

Hard mask removal process including isolation dielectric refill

Flash memory device

Etch damage repair with thermal annealing

Nitrogen implant after bit-line formation for ONO flash memory devices

Method of forming ONO flash memory devices using rapid thermal oxidation

Hard mask process for memory device without bitline shorts

Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells

Species implantation for minimizing interface defect density in flash memory devices

Method of fabricating a floating gate

Species implantation for minimizing interface defect density in flash memory devices

Structure and method for reducing charge loss in a memory cell

SPANSION LLC

Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer

System and method for improving mesa width in a semiconductor device

Avoiding field oxide gouging in shallow trench isolation (STI) regions

Memory structure having tunable interlayer dielectric and method for fabricating same

Method and device for reducing interface area of a memory device

Flash memory device and method of forming the same with improved gate breakdown and endurance

MACRONIX INT CO LTD

Non-volatile memory and fabricating method thereof

Method of fabricating memory

Non-volatile memory and fabricating method thereof

Method of fabricating memory

WU YIDER

System and method for improving reliability in a semiconductor device

System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device

Manufacturing method of flash memory structure with stress area

EON SILICON SOLUTION INC

Semiconductor memory structure with stress regions

Method for manufacturing nonvolatile semiconductor memory device structure

Single-poly non-volatile memory

FASL LLC

Dummy wordline for erase and bitline leakage

Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance