Inventor
VANDERPOOL BRIAN T
US38 patents
⚠️ This page may combine multiple inventors who share the name “VANDERPOOL BRIAN T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
32 patentsUS6754858B2Jun 22, 2004
SDRAM address error detection method and apparatus
IBM72 citations98
US7010654B2Mar 7, 2006
Methods and systems for re-ordering commands to access memory
IBM20 citations91
US7519510B2Apr 14, 2009
Derivative performance counter mechanism
IBM13 citations81
US7577793B2Aug 18, 2009
Patrol snooping for higher level cache eviction candidate identification
IBM7 citations74
US6836831B2Dec 28, 2004
Independent sequencers in a DRAM control structure
IBM8 citations74
US9684618B2Jun 20, 2017
Peripheral component interconnect express (PCIe) ping in a switch-based environment
IBM4 citations73
US9563591B2Feb 7, 2017
Peripheral component interconnect express (PCIe) ping in a switch-based environment
IBM2 citations73
US7650259B2Jan 19, 2010
Method for tuning chipset parameters to achieve optimal performance under varying workload types
IBM7 citations73
US7392353B2Jun 24, 2008
Prioritization of out-of-order data transfers on shared data bus
IBM8 citations73
US9832030B2Nov 28, 2017
Multicast packet routing via crossbar bypass paths
IBM3 citations72
US9571292B2Feb 14, 2017
Multicast packet routing via crossbar bypass paths
IBM2 citations72
US9479455B2Oct 25, 2016
Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar
IBM3 citations71
US9336169B2May 10, 2016
Facilitating resource use in multicycle arbitration for single cycle data transfer
IBM4 citations71
US9323703B2Apr 26, 2016
Facilitating resource use in multicyle arbitration for single cycle data transfer
IBM4 citations71
US8984206B2Mar 17, 2015
Weightage-based scheduling for hierarchical switching fabrics
IBM6 citations71
US8902899B2Dec 2, 2014
Input buffered switching device including bypass logic
IBM2 citations62
US7890708B2Feb 15, 2011
Prioritization of out-of-order data transfers on shared data bus
IBM5 citations62
US7536514B2May 19, 2009
Early return indication for read exclusive requests in shared memory architecture
IBM5 citations62
US8010682B2Aug 30, 2011
Early coherency indication for return data in shared memory architecture
IBM4 citations61
US6801982B2Oct 5, 2004
Read prediction algorithm to provide low latency reads with SDRAM cache
IBM4 citations61
US7761669B2Jul 20, 2010
Memory controller granular read queue dynamic optimization of command selection
IBM5 citations60
US9178832B2Nov 3, 2015
Queue credit management
IBM3 citations58
US9678906B2Jun 13, 2017
Oldest link first arbitration between links grouped as single arbitration elements
IBM0 citations51
US9678907B2Jun 13, 2017
Oldest link first arbitration between links grouped as single arbitration elements
IBM0 citations51
US9467396B2Oct 11, 2016
Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar
IBM0 citations50
US8879553B2Nov 4, 2014
Multicast bandwidth multiplication for a unified distributed switch
IBM0 citations50
US9444758B2Sep 13, 2016
Selective underflow protection in a network switch
IBM0 citations48
US9419912B2Aug 16, 2016
Selective underflow protection in a network switch
IBM0 citations48
US9207999B2Dec 8, 2015
Integrated link-based data recorder for semiconductor chip
IBM0 citations46
US9110742B2Aug 18, 2015
Integrated link-based data recorder for semiconductor chip
IBM0 citations46
US9722810B2Aug 1, 2017
Computer-based flow synchronization for efficient multicast forwarding for products and services
IBM0 citations41
US9667564B2May 30, 2017
Implementing hierarchical high radix switch with timesliced crossbar
IBM0 citations40