Inventor

MA YI

US94 patents

⚠️ This page may combine multiple inventors who share the name “MA YI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MA YI

LUCENT TECHNOLOGIES INC

Use of SiD4 for deposition of ultra thin and controllable oxides

System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor

Method for forming a high quality ultrathin gate oxide layer

Oxide/nitride stacked gate dielectric and associated methods

In-situ boron doped polysilicon with dual layer and dual grain structure for use in integrated circuits manufacturing

Polycide gate structure with intermediate barrier

Layered silicon nitride deposition process

Method of manufacturing semiconductor devices having high pressure anneal

Method for developing images in energy sensitive materials

Integrated circuit fabrication

Process for semiconductor device fabrication

Method of making a dielectric for an integrated circuit

Semiconductor device fabrication

Integrated circuit fabrication

Method for forming a nitride layer suitable for use in advanced gate dielectric materials

AGERE SYST GUARDIAN CORP

Gate structure for integrated circuit fabrication

System and method for forming a uniform thin gate oxide layer

Layered dielectric film structure suitable for gate dielectric application in sub-0.25 μm technologies

System and method for forming a uniform thin gate oxide layer

Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water

Semiconductor device, trench isolation structure and methods of formations

Silicon-germanium transistor and associated methods

Process for forming a plasma nitride film suitable for gate dielectric application in sub-0.25 μm technologies

N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure

AGERE SYSTEMS INC

Heterojunction bipolar transistor

Compound, high-K, gate and capacitor insulator layer

Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor

Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer

APPLIED MATERIALS INC

Atomic layer deposition processes for non-volatile memory devices

Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices

Atomic layer deposition processes for non-volatile memory devices

Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal

MA YI

Robust recovery of transform invariant low-rank textures

Conducting bridge random access memory (CBRAM) device structures

Recognition via high-dimensional data classification

LEE WEI TI

Resistive switching devices having a buffer layer and methods of formation thereof

Resistive switching devices having alloyed electrodes and methods of formation thereof

UNIV SHANGHAI TECHNOLOGY

Calibration method and apparatus for panoramic stereo video system

Stitching method and apparatus for panoramic stereo video system

OMNIVISION TECH INC

Biased deep trench isolation

Biased deep trench isolation

BOTBOTBOTBOT INC

Generating additional training data for a natural language understanding engine

SHENZHEN NEARBYEXPRESS TECH DEVELOPMENT COMPANY LIMITED

Mobile power bank

SHENZHEN LI ZHONG XIANG TECH CO LTD

Smart table lamp

ZHANG XIN

Rectification of characters and text as transform invariant low-rank textures

SPANSION LLC

Hetero-structure variable silicon rich nitride for multiple level memory flash memory device

GOPALAN CHAKRAVARTHY

Programmable impedance elements and devices that include such elements

ZHANG ZHENGDONG

Camera calibration with lens distortion from low-rank textures

REN ZHIFENG

Methods for high figure-of-merit in nanostructured thermoelectric materials

GALLO ANTONIO R

Variable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same