Inventor

GEISS ERIK

US6 patents

⚠️ This page may combine multiple inventors who share the name “GEISS ERIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLOBALFOUNDRIES INC

3 patents

US9397004B2Jul 19, 2016

Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings

GLOBALFOUNDRIES INC10 citations82

US10475890B2Nov 12, 2019

Scaled memory structures or other logic devices with middle of the line cuts

GLOBALFOUNDRIES INC2 citations73

US10707175B2Jul 7, 2020

Asymmetric overlay mark for overlay measurement

GLOBALFOUNDRIES INC3 citations72

BAARS PETER

1 patent

US8927407B2Jan 6, 2015

Method of forming self-aligned contacts for a semiconductor device

BAARS PETER9 citations83

WEI ANDY

1 patent

US8614123B2Dec 24, 2013

Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures

WEI ANDY7 citations83

GLOBAL FOUNDRIES INC

1 patent

US7601641B1Oct 13, 2009

Two step optical planarizing layer etch

GLOBAL FOUNDRIES INC10 citations82