Inventor

CHOI DONG-MYUNG

KR25 patents

⚠️ This page may combine multiple inventors who share the name “CHOI DONG-MYUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI DONG-MYUNG

MICRON TECHNOLOGY INC

Delay stage-interweaved analog DLL/PLL

Delay stage-interweaved analog DLL/PLL

Low power and low timing jitter phase-lock loop and method

Delay stage-interweaved analog DLL/PLL

Low power and low timing jitter phase-lock loop and method

Low power and low timing jitter phase-lock loop and method

Delay stage-interweaved analog DLL/PLL

Delay stage-interweaved analog DLL/PLL

Low power and low timing jitter phase-lock loop and method

Low power and low timing jitter phase-lock loop and method

SAMSUNG SDI CO LTD

Electrolyte and rechargeable lithium battery including same

Rechargeable lithium battery and method of fabricating same

Organic electrolyte solution including thiophene-based compound and nitrile-based compound and lithium battery comprising the same

Additive for electrolyte and electrolyte and lithium secondary battery

Additive for electrolyte and electrolyte and rechargeable lithium battery

Rechargeable lithium battery and method of fabricating the same

SAMSUNG ELECTRONICS CO LTD

Charge pump for adaptively controlling current offset

Method and apparatus for generating an eight-to-fourteen modulation data restoring clock signal

Phase locked loop for stable clock generation in applications of wide band channel clock recovery and operation method thereof

NVIDIA CORP

Circuit for implementing a continuous-time deglitching technique for digital analog converters

Window-enabled time-to-digital converter and method of detecting phase of a reference signal

System and method for increasing a voltage range associated with a voltage controlled oscillator

NAT SEMICONDUCTOR CORP

Adaptive frequency variable delay-locked loop

ALTERA CORP

Techniques for generating clock signals using oscillators

ROUND ROCK RES LLC

Low power and low timing jitter phase-lock loop and method