Inventor

SCHMATZ MARTIN L

CH45 patents

⚠️ This page may combine multiple inventors who share the name “SCHMATZ MARTIN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHMATZ MARTIN L

IBM

Low-power, low-area high-speed receiver architecture

Method for determining jitter of a signal in a serial link and high speed serial link

Phase locked loop and method for adjusting the frequency and phase in the phase locked loop

Phase locked loop and method for adjusting the frequency and phase in the phase locked loop

One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery

Adjustment of PLL bandwidth for jitter control using feedback circuitry

Clock and data recovery system and method for clock and data recovery based on a forward error correction

System, method and storage medium for deriving clocks in a memory system

Device for high density connections

Optimization of virtual machine sizing and consolidation

Distributed operating system functions for nodes in a rack

Optimization of virtual machine sizing and consolidation

Optical land grid array interposer

Optimizing tail latency via workload and resource redundancy in cloud

Method of forming a printed circuit board assembly

Assembly of printed circuit boards

Method and apparatus for generating random jitter

Method and system for data and edge detection with correlation tables

Digital adaptive control loop for data deserialization

Optimizing tail latency via workload and resource redundancy in cloud

Dynamic block intervals for pre-processing work items to be processed by processing elements

Dynamic measurement of communication channel characteristics using direct sequence spread spectrum (DSSS) systems, methods and program products

Methods and computer systems of software level superscalar out-of-order processing

Methods and computer systems of software level superscalar out-of-order processing

Clock and data recovery system and method for clock and data recovery based on a forward error correction

Using statistical signatures for testing high-speed circuits

Method and system for using statistical signatures for testing high-speed circuits

Integrated line driver

Multiplexer and demultiplexer

Persistent caching for operating a persistent caching system

Dynamic block intervals for pre-processing work items to be processed by processing elements

Fast detection of incorrect sampling in an oversampling clock and data recovery system

Deriving clocks in a memory system

Memory sharing by processors

Controlling power consumption

method for providing automatic adaptation to frequency offsets in high speed serial links

Method and system for performance ticket reduction

Detection of resource contention on computerized systems using co-located computer processes such as virtual machines

BUCHMANN PETER

Error correcting code protected quasi-static bit communication on a high-speed bus

Error correcting code protected quasi-static bit communication on a high-speed bus

KULL LUKAS

Structure for a reference voltage generator for analog to digital converters

BUCHMANN PETER L

Power-on initialization and test for a cascade interconnect memory system

BONACCIO ANTHONY R

Off-line gain calibration in a time-interleaved analog-to-digital converter

GLOBALFOUNDRIES INC

Memory module and memory controller for controlling a memory module

DREPS DANIEL M

Communications system via data scrambling and associated methods