Inventor
GEORGE GREGORY
US36 patents
⚠️ This page may combine multiple inventors who share the name “GEORGE GREGORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SUSS MICROTEC LITHOGRAPHY GMBH
16 patentsUS7948034B2May 24, 2011
Apparatus and method for semiconductor bonding
SUSS MICROTEC LITHOGRAPHY GMBH27 citations90
US8366873B2Feb 5, 2013
Debonding equipment and methods for debonding temporary bonded wafers
SUSS MICROTEC LITHOGRAPHY GMBH14 citations84
US8950459B2Feb 10, 2015
Debonding temporarily bonded semiconductor wafers
SUSS MICROTEC LITHOGRAPHY GMBH10 citations81
US10825705B2Nov 3, 2020
Apparatus, system, and method for handling aligned wafer pairs
SUSS MICROTEC LITHOGRAPHY GMBH2 citations72
US9875917B2Jan 23, 2018
Semiconductor bonding apparatus and related techniques
SUSS MICROTEC LITHOGRAPHY GMBH2 citations72
US9281229B2Mar 8, 2016
Method for thermal-slide debonding of temporary bonded semiconductor wafers
SUSS MICROTEC LITHOGRAPHY GMBH3 citations71
US9859141B2Jan 2, 2018
Apparatus and method for aligning and centering wafers
SUSS MICROTEC LITHOGRAPHY GMBH2 citations70
US9837295B2Dec 5, 2017
Apparatus and method for semiconductor wafer leveling, force balancing and contact sensing
SUSS MICROTEC LITHOGRAPHY GMBH3 citations70
US9583374B2Feb 28, 2017
Debonding temporarily bonded semiconductor wafers
SUSS MICROTEC LITHOGRAPHY GMBH4 citations70
US9472437B2Oct 18, 2016
Debonding temporarily bonded semiconductor wafers
SUSS MICROTEC LITHOGRAPHY GMBH4 citations70
US10825701B2Nov 3, 2020
Baking device for a wafer coated with a coating containing a solvent
SUSS MICROTEC LITHOGRAPHY GMBH2 citations69
US11651983B2May 16, 2023
Apparatus, system, and method for handling aligned wafer pairs
SUSS MICROTEC LITHOGRAPHY GMBH0 citations62
US11183401B2Nov 23, 2021
System and related techniques for handling aligned substrate pairs
SUSS MICROTEC LITHOGRAPHY GMBH0 citations55
US10319615B2Jun 11, 2019
Semiconductor bonding apparatus and related techniques
SUSS MICROTEC LITHOGRAPHY GMBH0 citations51
US9640418B2May 2, 2017
Apparatus, system, and method for handling aligned wafer pairs
SUSS MICROTEC LITHOGRAPHY GMBH0 citations51
US10580678B2Mar 3, 2020
Apparatus and method for semiconductor wafer leveling, force balancing and contact sensing
SUSS MICROTEC LITHOGRAPHY GMBH0 citations49
GEORGE GREGORY
9 patentsUS8551291B2Oct 8, 2013
Debonding equipment and methods for debonding temporary bonded wafers
GEORGE GREGORY16 citations92
US8267143B2Sep 18, 2012
Apparatus for mechanically debonding temporary bonded semiconductor wafers
GEORGE GREGORY23 citations90
US8147630B2Apr 3, 2012
Method and apparatus for wafer bonding with enhanced wafer mating
GEORGE GREGORY19 citations84
US8139219B2Mar 20, 2012
Apparatus and method for semiconductor wafer alignment
GEORGE GREGORY15 citations84
US8764026B2Jul 1, 2014
Device for centering wafers
GEORGE GREGORY8 citations79
US8425715B2Apr 23, 2013
Apparatus for high throughput wafer bonding
GEORGE GREGORY3 citations62
US8919412B2Dec 30, 2014
Apparatus for thermal-slide debonding of temporary bonded semiconductor wafers
GEORGE GREGORY3 citations60
US8574398B2Nov 5, 2013
Apparatus and method for detaping an adhesive layer from the surface of ultra thin wafers
GEORGE GREGORY1 citations52
US9064686B2Jun 23, 2015
Method and apparatus for temporary bonding of ultra thin wafers
GEORGE GREGORY1 citations49
INTEL CORP
5 patentsUS12426247B2Sep 23, 2025
Capacitor connections in dielectric layers
INTEL CORP0 citations61
US11991873B2May 21, 2024
Capacitor separations in dielectric layers
INTEL CORP0 citations61
US11832438B2Nov 28, 2023
Capacitor connections in dielectric layers
INTEL CORP0 citations61
US11610894B2Mar 21, 2023
Capacitor separations in dielectric layers
INTEL CORP0 citations61
US11652047B2May 16, 2023
Intermediate separation layers at the back-end-of-line
INTEL CORP0 citations50