Inventor
CACHARELIS PHILIP J
US5 patents
Patents
5 patentsUS5899714AMay 4, 1999
Fabrication of semiconductor structure having two levels of buried regions
NAT SEMICONDUCTOR CORP207 citations96
US5889315AMar 30, 1999
Semiconductor structure having two levels of buried regions
NAT SEMICONDUCTOR CORP231 citations96
US5108939AApr 28, 1992
Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
NAT SEMICONDUCTOR CORP68 citations95
US5550072AAug 27, 1996
Method of fabrication of integrated circuit chip containing EEPROM and capacitor
NAT SEMICONDUCTOR CORP48 citations91
US5591658AJan 7, 1997
Method of fabricating integrated circuit chip containing EEPROM and capacitor
NAT SEMICONDUCTOR CORP32 citations90