Inventor
KAHLE JAMES A
US36 patents
⚠️ This page may combine multiple inventors who share the name “KAHLE JAMES A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
30 patentsUS5913925AJun 22, 1999
Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
IBM175 citations98
US5467473ANov 14, 1995
Out of order instruction load and store comparison
IBM195 citations98
US6212542B1Apr 3, 2001
Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
IBM228 citations97
US5802386ASep 1, 1998
Latency-based scheduling of instructions in a superscalar processor
IBM114 citations97
US5867684AFeb 2, 1999
Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction
IBM30 citations92
US5694565ADec 2, 1997
Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions
IBM34 citations92
US5539681AJul 23, 1996
Circuitry and method for reducing power consumption within an electronic circuit
IBM21 citations91
US5420808AMay 30, 1995
Circuitry and method for reducing power consumption within an electronic circuit
IBM39 citations91
US5075840ADec 24, 1991
Tightly coupled multiprocessor instruction synchronization
IBM36 citations91
US5465373ANov 7, 1995
Method and system for single cycle dispatch of multiple instructions in a superscalar processor system
IBM46 citations89
US11016908B2May 25, 2021
Distributed directory of named data elements in coordination namespace
IBM5 citations73
US10049061B2Aug 14, 2018
Active memory device gather, scatter, and filter
IBM3 citations73
US11561844B2Jan 24, 2023
Disaggregated system domain
IBM2 citations71
US11288194B2Mar 29, 2022
Global virtual address space consistency model
IBM2 citations71
US11275614B2Mar 15, 2022
Dynamic update of the number of architected registers assigned to software threads using spill counts
IBM0 citations63
US9218291B2Dec 22, 2015
Implementing selective cache injection
IBM2 citations63
US12481796B2Nov 25, 2025
Secure memory sharing
IBM0 citations62
US11256507B2Feb 22, 2022
Thread transition management
IBM0 citations62
US11144231B2Oct 12, 2021
Relocation and persistence of named data elements in coordination namespace
IBM0 citations62
US10831663B2Nov 10, 2020
Tracking transactions using extended memory features
IBM1 citations62
US11288208B2Mar 29, 2022
Access of named data elements in coordination namespace
IBM1 citations60
US10915460B2Feb 9, 2021
Coordination namespace processing
IBM1 citations60
US10296339B2May 21, 2019
Thread transition management
IBM0 citations52
US10120810B2Nov 6, 2018
Implementing selective cache injection
IBM0 citations52
US10055226B2Aug 21, 2018
Thread transition management
IBM0 citations52
US9910783B2Mar 6, 2018
Implementing selective cache injection
IBM0 citations52
US9703561B2Jul 11, 2017
Thread transition management
IBM0 citations52
US9582427B2Feb 28, 2017
Implementing selective cache injection
IBM0 citations52
US12177031B2Dec 24, 2024
Enhanced endpoint multicast emulation
IBM0 citations50
US9064030B2Jun 23, 2015
Tree traversal in a memory device
IBM0 citations41