Inventor

PETRARCA KEVIN S

US98 patents

⚠️ This page may combine multiple inventors who share the name “PETRARCA KEVIN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PETRARCA KEVIN S

IBM

Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material

Perpendicular torsion micro-electromechanical switch

Method of fabricating micro-electromechanical switches on CMOS compatible substrates

Micro electromechanical switch having self-aligned spacers

Common ball-limiting metallurgy for I/O sites

Multilevel interconnect structure containing air gaps and method for making

Selective plating process

Pattern-sensitive electrolytic metal plating

Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via

Multilayer interconnect structure containing air gaps and method for making

Production of metal insulator metal (MIM) structures using anodizing process

Method of forming a crack stop structure and diffusion barrier in integrated circuits

RFID tag with environmental sensor

Fuse link structures using film stress for programming and methods of manufacture

Wire bonding personalization and discrete component attachment on wirebond pads

Semiconductor devices containing a discontinuous cap layer and methods for forming same

Fuse structure and method to form the same

Method of fabricating micro-electromechanical switches on CMOS compatible substrates

Encapsulated metal structures for semiconductor devices and MIM capacitors including the same

Encapsulated metal structures for semiconductor devices and MIM capacitors including the same

Microprocessor having air as a dielectric and encapsulated lines and process for manufacture

Method of forming a patterned organic dielectric layer on a substrate

MEMS encapsulated structure and method of making same

Front side wafer ID processing

Self-aligned patterned etch stop layers for semiconductor devices

Method of fabricating a high Q factor integrated circuit inductor

Method for forming C4 connections on integrated circuit chips and the resulting devices

Structure and method for hybrid tungsten copper metal contact

Planar vertical resistor and bond pad resistor and related method

Forming of high aspect ratio conductive structure using injection molded solder

High Q factor integrated circuit inductor

Multi-level RF passive device

Protected through semiconductor via (TSV)

Structure and method for reducing thermo-mechanical stress in stacked vias

Hybrid bonding interface for 3-dimensional chip integration

Method to create air gaps using non-plasma processes to damage ILD materials

Planar vertical resistor and bond pad resistor

Production of metal insulator metal (MIM) structures using anodizing process

Fuse structure and method to form the same

Self-contained heat sink and a method for fabricating same

FAROOQ MUKTA G

Soft error rate mitigation by interconnect structure

TSV pillar as an interconnecting structure

Alignment marks to enable 3D integration

Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip

BARTH KARL W

Fuse link structures using film stress for programming and methods of manufacture

Fuse link structures using film stress for programming and methods of manufacture

Hybrid bonding interface for 3-dimensional chip integration

VOLANT RICHARD P

Method of fabricating coaxial through-silicon via

Coaxial through-silicon via

CLEVENGER LAWRENCE A

Electrically contactable grids manufacture