Inventor · disambiguated record
Bernd Kastenmeier
Also filed as: KASTENMEIER BERND · KASTENMEIER BERND E · KASTENMEIER BERND E E · KASTENMEIER BERND ERNST EDUARD
10 granted patents·2 pending applications·159 citations·filing 1998–2013
89Inventor score
Top patents by PatentIndex Score
12 records- 0192US7256148B2Method for treating a wafer edgeIBM·Filed 2005·Granted Aug 14, 2007·21 cites·13 claims
- 0283US6060400AHighly selective chemical dry etching of silicon nitride over silicon and silicon dioxideUNIV NEW YORK STATE RES FOUND·Filed 1998·Granted May 9, 2000·79 cites·11 claims
- 0372US6831363B2Structure and method for reducing thermo-mechanical stress in stacked viasIBM·Filed 2002·Granted Dec 14, 2004·18 cites·15 claims
- 0468US7125782B2Air gaps between conductive lines for reduced RC delay of integrated circuitsIBM·Filed 2004·Granted Oct 24, 2006·15 cites·37 claims
- 0566US7943453B2CMOS devices with different metals in gate electrodes using spin on low-k material as hard maskIBM·Filed 2007·Granted May 17, 2011·3 cites·13 claims
- 0665US7157373B2Sidewall sealing of porous dielectric materialsIBM·Filed 2003·Granted Jan 2, 2007·13 cites·18 claims
- 0762US8987862B2Methods of forming semiconductor devices having conductors with different dimensionsKASTENMEIER BERND E·Filed 2011·Granted Mar 24, 2015·4 cites·18 claims
- 0851US7214608B2Interlevel dielectric layer and metal layer sealingIBM·Filed 2004·Granted May 8, 2007·4 cites·20 claims
- 0949US6613484B2Method to decrease fluorine contamination in low dielectric constant filmsIBM·Filed 2001·Granted Sep 2, 2003·2 cites·16 claims
- 1045US2009004865A1Method for treating a wafer edgeKASTENMEIER BERND E E·Filed 2007·Application pending·0 cites
- 1138US9846758B2Method of designing an integrated circuit and computer program productHOURS XAVIER·Filed 2013·Granted Dec 19, 2017·0 cites·13 claims
- 1237US2005176237A1In-situ liner formation during reactive ion etchFiled 2004·Application pending·0 cites
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