Inventor

CHAN BOON TEIK

BE48 patents

⚠️ This page may combine multiple inventors who share the name “CHAN BOON TEIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAN BOON TEIK

IMEC VZW

Method for producing fin structures of a semiconductor device in a substrate

Method for pattern formation on a substrate, associated semiconductor devices, and uses of the method

Method of fabricating stacked semiconductor device

Method for blocking a trench portion

Method for patterning a substrate involving directed self-assembly

Method for forming a field effect transistor device having an electrical contact

Isolated semiconductor layer stacks for a semiconductor device

Self-aligned layer patterning

Method for forming a buried metal line

Contact isolation in semiconductor devices

Method for filling a space in a semiconductor

Method for processing a semiconductor device with two closely spaced gates

Methods of semiconductor device processing

Removing an organic sacrificial material from a two-dimensional material

Method for forming a stacked transistor device

FET device and a method for forming a FET device

Method for processing a FinFET device

Method for forming a semiconductor device and a semiconductor device

Method for producing a gate cut structure on an array of semiconductor fins

Vertical nanowire semiconductor structures

Method for forming a semiconductor device

Method for forming a stacked FET device

Method for forming a semiconductor device

Method for forming a buried metal line in a semiconductor substrate

Method of forming a mask layer

Metal of ceramic material hardened pattern

Method of forming internal spacer for nanowires

Metallization method for semiconductor structures

Gate spacer patterning

Method for forming transistor structures

Split replacement metal gate integration

Method for producing fin structures of a semiconductor device in a substrate

Method for forming a stacked FET device

Circuit cell for a standard cell semiconductor device

Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor

Method of forming micro-pipes on a substrate and a structure formed thereof

Conductive via formation connecting transistor structures in an integrated circuit

Bit cell with isolating wall

Self-aligned nanostructures for semiconductor devices

Method for producing a pillar structure in a semiconductor layer

Area-selective deposition of a tantalum silicide TaSix mask material

Reticles for lithography

Method for forming contact vias

Method for forming horizontal nanowires and devices manufactured thereof

Method for patterning an underlying layer

IMEC

Method for block-copolymer lithography

Etching method using block-copolymers

CHAN BOON TEIK

Method for plasma texturing