Inventor

KIM RYAN RYOUNG HAN

BE40 patents

⚠️ This page may combine multiple inventors who share the name “KIM RYAN RYOUNG HAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM RYAN RYOUNG HAN

GLOBALFOUNDRIES INC

Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Single and double diffusion breaks on integrated circuit products comprised of FinFET devices

Gate contact structure having gate contact layer

Vertical channel transistor-based semiconductor memory structure

SAV using selective SAQP/SADP

Method for producing self-aligned vias

Methods for fabricating integrated circuits using self-aligned quadruple patterning

Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithography

Methods of forming reduced resistance local interconnect structures and the resulting devices

Method of utilizing trench silicide in a gate cross-couple construct

Buried fin contact structures on FinFET semiconductor devices

Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices

Methods of forming contact structures on finfet semiconductor devices and the resulting devices

Dummy gate used as interconnection and method of making the same

Methods for fabricating integrated circuits using self-aligned quadruple patterning

Vertical transistor static random access memory cell

Method of utilizing trench silicide in a gate cross-couple construct

Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines

Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines

Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product

Merged source/drain and gate contacts in SRAM bitcell

Multilayer interconnect structure and method for integrated circuits

Methods for fabricating integrated circuits including selectively forming and removing fin structures

Contact formation for semiconductor device

Metal segments as landing pads and local interconnects in an IC device

Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material

Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein

Methods of forming features having differing pitch spacing and critical dimensions

Method of utilizing trench silicide in a gate cross-couple construct

Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes

Dummy gate used as interconnection and method of making the same

Shrink process aware assist features

Semiconductor device configured for avoiding electrical shorting

IMEC VZW

Methods for forming conductive paths and vias

Method for analyzing design of an integrated circuit

Method for forming a via hole self-aligned with a metal block on a substrate

Mask for extreme-ultraviolet (extreme-UV) lithography and method for manufacturing the same

Method for producing a gate cut structure on an array of semiconductor fins

GLOBALFOUNDIES INC

Methods of forming FinFET devices in different regions of an integrated circuit product