Inventor

BERGENDAHL MARC A

US93 patents

⚠️ This page may combine multiple inventors who share the name “BERGENDAHL MARC A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BERGENDAHL MARC A

IBM

BEOL vertical fuse formed over air gap

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Formation of a bottom source-drain for vertical field-effect transistors

Single spacer for complementary metal oxide semiconductor process flow

FinFETs and fin isolation structures

Gate cut with integrated etch stop layer

Sub-lithographic semiconductor structures with non-constant pitch

Single fin cut employing angled processing methods

Metal alloy cap integration

Hybrid airgap structure with oxide liner

Selective dielectric deposition to prevent gouging in MRAM

Nanosheet channel-to-source and drain isolation

Nanosheet channel-to-source and drain isolation

Fin patterns with varying spacing without fin cut

Forming stacked nanowire semiconductor device

Air gap spacer for metal gates

Vertical transport field effect transistor with precise gate length definition

Hybrid airgap structure with oxide liner

Dummy gate formation using spacer pull down hardmask

Metal alloy cap integration

Structure of UBM and solder bumps and methods of fabrication

Sublithography gate cut physical unclonable function

Super long channel device within VFET architecture

Gate cut with integrated etch stop layer

Air gap spacer for metal gates

Multi-angled deposition and masking for custom spacer trim and selected spacer removal

Formation of a bottom source-drain for vertical field-effect transistors

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Fin patterns with varying spacing without fin cut

Fin patterns with varying spacing without fin cut

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Fin patterns with varying spacing without fin cut

Dummy gate formation using spacer pull down hardmask

Method and structure to enable dual channel fin critical dimension control

Single spacer for complementary metal oxide semiconductor process flow

BEOL capacitor through airgap metallization

Substrate isolated VTFET devices

Semiconductor device with linerless contacts

TESSERA LLC

Gate cut with integrated etch stop layer

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

Gate cut with integrated etch stop layer

TESSERA INC

Nanosheet channel-to-source and drain isolation

Gate cut with integrated etch stop layer

Air gap spacer for metal gates

GLOBALFOUNDRIES INC

Sub-lithographic semiconductor structures with non-constant pitch

Mask free protection of work function material portions in wide replacement gate electrodes

KOBURGER III CHARLES W

Mask free protection of work function material portions in wide replacement gate electrodes