Inventor

NAYAK DEEPAK KUMAR

IN23 patents

⚠️ This page may combine multiple inventors who share the name “NAYAK DEEPAK KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAYAK DEEPAK KUMAR

XILINX INC

Method of fabricating strain-silicon CMOS

Strain-silicon CMOS with dual-stressed film

Semiconductor device and process for improved etch control of strained silicon alloy trenches

Method of fabricating strain-silicon CMOS

Strain-silicon CMOS using etch-stop layer and method of manufacture

Semiconductor device with backfilled isolation

Strain-silicon CMOS using etch-stop layer and method of manufacture

Method of forming silicide gate with interlayer

Method of and circuit for protecting a transistor formed on a die

CMOS device with stressed sidewall spacers

NOKIA SOLUTIONS & NETWORKS OY

Beam selection for cellular access nodes

Beam configuration optimization

Beam and antenna array split configuration optimization

Efficient data generation for beam pattern optimization

Method for determining beam interference

AMAZON TECH INC

Techniques for generating machine learning training data

Taxonomy generation with statistical analysis and auditing

Classification accuracy estimation

ADVANCED MICRO DEVICES INC

Method to optimize p-channel CMOS ICs using Qbd as a monitor of boron penetration

Method and circuit for detecting boron (&#34;B&#34;) in a semiconductor device using threshold voltage (&#34;V&#34;) fluence test

Reducing reverse short-channel effect with light dose of P with high dose of as in n-channel LDD

LUO YUHAO

Semiconductor device with improved trenches

GLOBALFOUNDRIES INC

High mobility PMOS and NMOS devices having Si—Ge quantum wells

Method and circuit for detecting boron ("B") in a semiconductor device using threshold voltage ("V") fluence test