Inventor

ROSENBLUTH MARK B

US63 patents

⚠️ This page may combine multiple inventors who share the name “ROSENBLUTH MARK B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROSENBLUTH MARK B

INTEL CORP

Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment

Software controlled content addressable memory in a general purpose execution datapath

Method of implementing off-chip cache memory in dual-use SRAM memory for network processors

Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section

Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems

Multithreaded microprocessor with register allocation based on number of active threads

Memory interleaving

Control mechanisms for enqueue and dequeue operations in a pipelined network processor

Software controlled content addressable memory in a general purpose execution datapath

Queue management

Memory interleaving

Enqueue operations for multi-buffer packets

Graphical user interface for use during processor simulation

Heterogeneous processors sharing a common cache

Processing a data packet

Branch-aware FIFO for interprocessor data sharing

Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms

Context pipelines

Command ordering

Multiprocessor breakpoint

Methods and apparatus for supporting programmable burst management schemes on pipelined buses

Atomic operations in PCI express

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Caching for heterogeneous processors

Queue arrays in network devices

Data transfer mechanism using unidirectional pull bus and push bus

Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit

Registers for data transfers

Free list and ring data structure management

Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access

Queue array caching in network devices

Content addressable memory to identify subtag matches

Processing data packets

Write queue descriptor count instruction for high speed queuing

Caching bypass

Method and apparatus to communicate flow control information in a duplex network processor system

Scalable, two-stage round robin arbiter with re-circulation and bounded latency

Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency

Method and apparatus to assemble data segments into full packets for efficient packet-based classification

Caching for heterogeneous processors

Caching for heterogeneous processors

Techniques to manage flow control

HADY FRANK T

Heterogeneous processors sharing a common cache

Caching for heterogeneous processors

MELLANOX TECHNOLOGIES LTD

Hardware engine for configuration register setup

Write reordering in a multiprocessor system

GRIFFIN PATRICK ROBERT

Computing in parallel processing environments

DIGITAL EQUIPMENT CORP

Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay