Inventor

ZHOU ZHENMING

US161 patents

⚠️ This page may combine multiple inventors who share the name “ZHOU ZHENMING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHOU ZHENMING

MICRON TECHNOLOGY INC

Preread and read threshold voltage optimization

Optimized seasoning trim values based on form factors in memory sub-system manufacturing

Adjustment of read and write voltages using a space between threshold voltage distributions

Adapting an error recovery process in a memory sub-system

Managing threshold voltage drift based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system

Adaptive scanning of memory devices with supervised learning

Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system

Adaptive wear leveling for endurance compensation

Error avoidance for partially programmed blocks of a memory device

Adaptive sensing time for memory operations

Memory read operation using a voltage pattern based on a read command type

Open translation unit management using an adaptive read threshold

Managing a hybrid error recovery process in a memory sub-system

Managing write disturb based on identification of frequently-written memory units

Temperature-based media management for memory components

Dynamic voltage setting optimization during lifetime of a memory device

Managing write disturb for units of memory in a memory sub-system

Memory duty-cycle skew management

Selective power-on scrub of memory units

Decision for executing full-memory refresh during memory sub-system power-on stage

Managing threshold voltage drift based on operating characteristics of a memory sub-system

Performing a refresh operation based on system characteristics

Managing an adjustable write-to-read delay of a memory sub-system

Read level compensation for partially programmed blocks of memory devices

Dynamic read calibration

Charge loss mitigation through dynamic programming sequence

Corrective read with parallel auto-read calibration in a memory sub-system

Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system

Adaptive time sense parameters and overdrive voltage parameters for respective groups of wordlines in a memory sub-system

Power management for memory devices with partially good blocks

Programming delay scheme for in a memory sub-system based on memory reliability

Dynamic erase operation selection using erase policy

Adaptive sensing time for memory operations

Memory read operation using a voltage pattern based on a read command type

SANDISK TECHNOLOGIES INC

Word line dependent programming in a memory device

Recovery of partially programmed block in non-volatile memory

On chip dynamic read level scan and error detection for nonvolatile storage

On chip dynamic read level scan and error detection for nonvolatile storage

Smart verify for programming non-volatile memory

Partial block erase for data refreshing and open-block programming

Memory cells using multi-pass programming

Erased state reading

Internal data load for non-volatile storage

Read disturb detection in open blocks

SANDISK TECHNOLOGIES LLC

Non-volatile memory with bit line controlled multi-plane mixed sub-block programming

Managing bit-line settling time in non-volatile memory

State-dependent read compensation

Non-volatile memory with multi-plane mixed sub-block programming

Manage source line bias to account for non-uniform resistance of memory cell source lines

Manage source line bias to account for non-uniform resistance of memory cell source lines