Inventor
GAAN SANDEEP
US16 patents
⚠️ This page may combine multiple inventors who share the name “GAAN SANDEEP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
12 patentsUS9123771B2Sep 1, 2015
Shallow trench isolation integration methods and devices formed thereby
GLOBALFOUNDRIES INC13 citations82
US8940650B2Jan 27, 2015
Methods for fabricating integrated circuits utilizing silicon nitride layers
GLOBALFOUNDRIES INC4 citations72
US9385192B2Jul 5, 2016
Shallow trench isolation integration methods and devices formed thereby
GLOBALFOUNDRIES INC3 citations71
US9224842B2Dec 29, 2015
Patterning multiple, dense features in a semiconductor device using a memorization layer
GLOBALFOUNDRIES INC5 citations71
US9831098B2Nov 28, 2017
Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
GLOBALFOUNDRIES INC3 citations67
US9076645B1Jul 7, 2015
Method of fabricating an interlayer structure of increased elasticity modulus
GLOBALFOUNDRIES INC2 citations61
US9520395B2Dec 13, 2016
FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack
GLOBALFOUNDRIES INC2 citations60
US9502232B2Nov 22, 2016
Inhibiting diffusion of elements between material layers of a layered circuit structure
GLOBALFOUNDRIES INC0 citations51
US9184288B2Nov 10, 2015
Semiconductor structures with bridging films and methods of fabrication
GLOBALFOUNDRIES INC0 citations50
US9673039B2Jun 6, 2017
Devices comprising high-K dielectric layer and methods of forming same
GLOBALFOUNDRIES INC0 citations47
US9570291B2Feb 14, 2017
Semiconductor substrates and methods for processing semiconductor substrates
GLOBALFOUNDRIES INC0 citations42
US9466701B2Oct 11, 2016
Processes for preparing integrated circuits with improved source/drain contact structures and integrated circuits prepared according to such processes
GLOBALFOUNDRIES INC0 citations41
INTEL CORP
4 patentsUS11443885B2Sep 13, 2022
Thin film barrier seed metallization in magnetic-plugged through hole inductor
INTEL CORP4 citations72
US11387175B2Jul 12, 2022
Interposer package-on-package (PoP) with solder array thermal contacts
INTEL CORP6 citations72
US11037802B2Jun 15, 2021
Package substrate having copper alloy sputter seed layer and high density interconnects
INTEL CORP0 citations62
US11291122B2Mar 29, 2022
Apparatus with a substrate provided with plasma treatment
INTEL CORP0 citations58