Inventor

NAD SUDDHASATTWA

US33 patents

⚠️ This page may combine multiple inventors who share the name “NAD SUDDHASATTWA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAD SUDDHASATTWA

INTEL CORP

Circuit device with monolayer bonding between surface structures

Angled inductor with small form factor

High performance integrated RF passives using dual lithography process

Subtractive etch resolution implementing a functional thin metal resist

Customizable release layers to enable low warpage architectures for advanced packaging applications

In-situ component fabrication of a highly efficient, high inductance air core inductor integrated into substrate packages

Semiconductor package having polymeric interlayer disposed between conductive elements and dielectric layer

High performance integrated RF passives using dual lithography process

Package power delivery using plane and shaped vias

Package power delivery using plane and shaped vias

Surface functionalization of sinx thin film by wet etching for improved adhesion of metal-dielectric for HSIO

Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein

Conductive route patterning for electronic substrates

Hybrid fine line spacing architecture for bump pitch scaling

Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures

Package architecture with improved via drill process and method for forming such package

Defect-free through glass via metallization implementing a sacrificial resist thinning material

Microelectronic assemblies including interconnects with different solder materials

Dielectric-to-metal adhesion promotion material

Package architecture with tunable magnetic properties for embedded devices

Method, device and system for providing etched metallization structures

Method, device and system for providing etched metallization structures

Electronic packaging architecture with customized variable metal thickness on same buildup layer

Capacitors in through glass vias

Structural elements for application specific electronic device packages

Apparatus with a substrate provided with plasma treatment

Conductive route patterning for electronic substrates

Microelectronic assemblies having conductive structures with different thicknesses

Method for fabricating multiplexed hollow waveguides of variable type on a semiconductor package

Selective metal deposition by patterning direct electroless metal plating

Selectively roughened copper architectures for low insertion loss conductive features

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

THE INTEL CORP

Substrates having adhesion promotor layers and related methods