Inventor · disambiguated record
Ed Seewann
Also filed as: SEEWANN ED
5 granted patents·27 citations·filing 2005–2006
74Inventor score
Files withIBM5
Top patents by PatentIndex Score
5 records- 0175US7283404B2Content addressable memory including a dual mode cycle boundary latchIBM·Filed 2005·Granted Oct 16, 2007·11 cites·6 claims
- 0273US7167385B2Method and apparatus for controlling the timing of precharge in a content addressable memory systemIBM·Filed 2005·Granted Jan 23, 2007·9 cites·20 claims
- 0368US7116569B2Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare maskIBM·Filed 2005·Granted Oct 3, 2006·7 cites·20 claims
- 0443US7600071B2Circuit having relaxed setup time via reciprocal clock and data gatingIBM·Filed 2006·Granted Oct 6, 2009·0 cites·20 claims
- 0534US7501854B2True/complement generator having relaxed setup time via self-resetting circuitryIBM·Filed 2006·Granted Mar 10, 2009·0 cites·17 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →